Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals

ABSTRACT

The present invention provides a method of transmitting broadcast signals. The method includes, encoding, by an encoder, data in plural PLPs (Physical Layer Pipes); processing, by a framing and interleaving block, the encoded data in the plural PLPs, wherein the processing the encoded data further includes: time interleaving, by a time interleaver, the encoded data in the plural PLPs, frame mapping, by a framer, the time interleaved data onto at least one signal frame, and frequency interleaving, by a frequency interleaver, data in the at least one signal frame; and waveform modulating, by a waveform generation block, the frequency interleaved data in the at least one signal frame and transmitting, by the waveform generation block, broadcast signals having the waveform modulated data.

Pursuant to 35 U.S.C. §119(e), this application claims the benefit of U.S. Provisional Applications No. 62/108,065, filed on Jan. 27, 2015 and 62/134,546, filed on Mar. 17, 2015, which is hereby incorporated by reference as if fully set forth herein.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to an apparatus for transmitting broadcast signals, an apparatus for receiving broadcast signals and methods for transmitting and receiving broadcast signals.

Discussion of the Related Art

As analog broadcast signal transmission comes to an end, various technologies for transmitting/receiving digital broadcast signals are being developed. A digital broadcast signal may include a larger amount of video/audio data than an analog broadcast signal and further include various types of additional data in addition to the video/audio data. [3] That is, a digital broadcast system can provide HD (high definition) images, multi-channel audio and various additional services. However, data transmission efficiency for transmission of large amounts of data, robustness of transmission/reception networks and network flexibility in consideration of mobile reception equipment need to be improved for digital broadcast.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to an apparatus for transmitting broadcast signals and an apparatus for receiving broadcast signals for future broadcast services and methods for transmitting and receiving broadcast signals for future broadcast services.

An object of the present invention is to provide an apparatus and method for transmitting broadcast signals to multiplex data of a broadcast transmission/reception system providing two or more different broadcast services in a time domain and transmit the multiplexed data through the same RF signal bandwidth and an apparatus and method for receiving broadcast signals corresponding thereto.

Another object of the present invention is to provide an apparatus for transmitting broadcast signals, an apparatus for receiving broadcast signals and methods for transmitting and receiving broadcast signals to classify data corresponding to services by components, transmit data corresponding to each component as a data pipe, receive and process the data

Still another object of the present invention is to provide an apparatus for transmitting broadcast signals, an apparatus for receiving broadcast signals and methods for transmitting and receiving broadcast signals to signal signaling information necessary to provide broadcast signals.

To achieve the object and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the present invention provides a method of transmitting broadcast signals. The method of transmitting broadcast signals includes encoding, by an encoder, data in plural PLPs (Physical Layer Pipes); processing, by a framing and interleaving block, the encoded data in the plural PLPs, wherein the processing the encoded data further includes: time interleaving, by a time interleaver, the encoded data in the plural PLPs, frame mapping, by a framer, the time interleaved data onto at least one signal frame, and frequency interleaving, by a frequency interleaver, data in the at least one signal frame; and waveform modulating, by a waveform generation block, the frequency interleaved data in the at least one signal frame and transmitting, by the waveform generation block, broadcast signals having the waveform modulated data.

Preferably, the encoding data in plural PLPs further includes: encoding data in at least one of the PLPs at first layer, and encoding data in the other PLPs at second layer.

In other aspect, the present invention provides a method of receiving broadcast signals. The method of receiving broadcast signals includes receiving, by a waveform block, broadcast signals having at least one signal frame and demodulating, by the waveform block, data in the at least one signal frame; processing, by a parsing and deinterleaving block, the demodulated data in the at least one signal frame to output plural PLPs (Physical Layer Pipes), wherein the processing further includes: frequency deinterleaving, by a frequency deinterleaver, the demodulated data in the at least one signal frame, frame parsing, by a frame parser, the plural PLPs from the at least one signal frame, and

time deinterleaving, by a time deinterleaver, data in the plural PLPs; and decoding, by a decoder, the time deinterleaved data in the plural PLPs.

Preferably, the method further includes: spliting, by a spliting block, first layer and second layer from the time deinterleaved data in the plural PLPs before the decoding.

In another aspect, the present invention provides an appratus for transmitting broadcast signals. The appratus for transmitting broadcast signals includes an encoder that encodes data in plural PLPs (Physical Layer Pipes); a framing and interleaving block that processes the encoded data in the plural PLPs, wherein the framing and interleaving block further includes: a time interleaver that time interleaves the encoded data in the plural PLPs, a framer that frame maps the time interleaved data onto at least one signal frame, and a frequency interleaver that frequency interleaves data in the at least one signal frame; and a waveform generation block that waveform modulates the frequency interleaved data in the at least one signal frame and that transmits broadcast signals having the waveform modulated data.

Preferably, the encoder further includes: a first encoder that encodes data in at least one of the PLPs at first layer, and a second encoder that encodes data in the other PLPs at second layer.

In another aspect, the present invention provides an appratus for receiving broadcast signals. The apparatus for receiving broadcast signals includes a waveform block that receives broadcast signals having at least one signal frame and that demodulates data in the at least one signal frame; a parsing and deinterleaving block that processes the demodulated data in the at least one signal frame to output plural PLPs (Physical Layer Pipes), wherein the parsing and deinterleaving block further includes: a frequency deinterleaver that frequency deinterleaves the demodulated data in the at least one signal frame, a frame parser that frame parses the plural PLPs from the at least one signal frame, and a time deinterleaver that time deinterleaves data in the plural PLPs; and a decoder that decodes the time deinterleaved data in the plural PLPs.

Preferably, the apparatus further includes: a spliting block that splits first layer and second layer from the time deinterleaved data in the plural PLPs before the decoding.

The present invention can process data according to service characteristics to control QoS (Quality of Services) for each service or service component, thereby providing various broadcast services.

The present invention can achieve transmission flexibility by transmitting various broadcast services through the same RF signal bandwidth.

The present invention can improve data transmission efficiency and increase robustness of transmission/reception of broadcast signals using a MIMO system.

According to the present invention, it is possible to provide broadcast signal transmission and reception methods and apparatus capable of receiving digital broadcast signals without error even with mobile reception equipment or in an indoor environment.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. In the drawings:

FIG. 1 illustrates a structure of an apparatus for transmitting broadcast signals for future broadcast services according to an embodiment of the present invention.

FIG. 2 illustrates an input formatting block according to one embodiment of the present invention.

FIG. 3 illustrates an input formatting block according to another embodiment of the present invention.

FIG. 4 illustrates an input formatting block according to another embodiment of the present invention.

FIG. 5 illustrates a BICM block according to an embodiment of the present invention.

FIG. 6 illustrates a BICM block according to another embodiment of the present invention.

FIG. 7 illustrates a frame building block according to one embodiment of the present invention.

FIG. 8 illustrates an OFDM generation block according to an embodiment of the present invention.

FIG. 9 illustrates a structure of an apparatus for receiving broadcast signals for future broadcast services according to an embodiment of the present invention.

FIG. 10 illustrates a frame structure according to an embodiment of the present invention.

FIG. 11 illustrates a signaling hierarchy structure of the frame according to an embodiment of the present invention.

FIG. 12 illustrates preamble signaling data according to an embodiment of the present invention.

FIG. 13 illustrates PLS1 data according to an embodiment of the present invention.

FIG. 14 illustrates PLS2 data according to an embodiment of the present invention.

FIG. 15 illustrates PLS2 data according to another embodiment of the present invention.

FIG. 16 illustrates a logical structure of a frame according to an embodiment of the present invention.

FIG. 17 illustrates PLS mapping according to an embodiment of the present invention.

FIG. 18 illustrates EAC mapping according to an embodiment of the present invention.

FIG. 19 illustrates FIC mapping according to an embodiment of the present invention.

FIG. 20 illustrates a type of DP according to an embodiment of the present invention.

FIG. 21 illustrates DP mapping according to an embodiment of the present invention.

FIG. 22 illustrates an FEC structure according to an embodiment of the present invention.

FIG. 23 illustrates a bit interleaving according to an embodiment of the present invention.

FIG. 24 illustrates a cell-word demultiplexing according to an embodiment of the present invention.

FIG. 25 illustrates a time interleaving according to an embodiment of the present invention.

FIG. 26 illustrates the basic operation of a twisted row-column block interleaver according to an embodiment of the present invention.

FIG. 27 illustrates an operation of a twisted row-column block interleaver according to another embodiment of the present invention.

FIG. 28 illustrates a diagonal-wise reading pattern of a twisted row-column block interleaver according to an embodiment of the present invention.

FIG. 29 illustrates interlaved XFECBLOCKs from each interleaving array according to an embodiment of the present invention.

FIG. 30 is a diagram illustrating a configuration of an interleaver according to an embodiment of the present invention.

FIG. 31 illustrates a configuration of an interleaver according to an embodiment of the present invention when the PLP mode corresponds to M-PLP.

FIG. 32 illustrates a configuration of a deinterleaver corresponding to the operation of the interleaver described with reference to FIGS. 30 and 31.

FIG. 33 illustrates a shift value applicable to a cell interleaver according to another embodiment of the present invention and an interleaving sequent according to the shift value expressed as a mathematical expression.

FIG. 34 shows an equation indicating a twisted reading operation after virtual FEC blocks are inserted according to an embodiment of the present invention.

FIG. 35 shows an equation indicating a twisted read operation performed after virtual FEC blocks are inserted when a shift value is fixed to 1 according to an embodiment of the present invention.

FIG. 36 shows an equation indicating twisted block deinterleaving of a hybrid time deinterleaver according to an embodiment of the present invention.

FIG. 37 shows an equation indicating twisted block deinterleaving of a hybrid time deinterleaver according to an embodiment of the present invention.

FIG. 38 illustrates an operation of the hybrid time interleaver according to an embodiment of the present invention.

FIG. 39 illustrates an operation of the hybrid time interleaver according to an embodiment of the present invention.

FIG. 40 illustrates an operation of the hybrid time deinterleaver according to an embodiment of the present invention.

FIG. 41 illustrates an operation of the hybrid time deinterleaver according to an embodiment of the present invention.

FIG. 42 illustrates an operation of the hybrid time deinterleaver according to an embodiment of the present invention.

FIG. 43 illustrates a configuration of the CI according to an embodiment of the present invention.

FIG. 44 shows parameters used in a convolutional interleaver according to an embodiment of the present invention.

FIG. 45 illustrates a method of generating signaling information and a convolutional interleaver according to an embodiment of the present invention.

FIG. 46 illustrates a method of acquiring signaling information related to interleaving by a broadcast signal transmission apparatus according to an embodiment of the present invention.

FIG. 47 illustrates an operation of a convolutional interleaver according to an embodiment of the present invention.

FIG. 48 illustrates a method of configuring a frame by a convolutional interleaver according to an embodiment of the present invention.

FIG. 49 illustrates a method of configuring a frame by a convolutional interleaver according to an embodiment of the present invention.

FIG. 50 illustrates a configuration of a CDI according to an embodiment of the present invention.

FIG. 51 illustrates an operation method of a convolutional deinterleaver according to an embodiment of the present invention.

FIG. 52 illustrates an operation method of a convolutional deinterleaver according to an embodiment of the present invention.

FIG. 53 illustrates a time interleaver according to an embodiment of the present invention.

FIG. 54 illustrates a portion of time interleaving signaling information according to an embodiment of the present invention.

FIG. 55 illustrates the other portion of the time interleaving signaling information according to an embodiment of the present invention.

FIG. 56 illustrates a time deinterleaver according to an embodiment of the present invention. In other words,

FIG. 57 illustrates a portion of a configuration of a broadcast signal transmission apparatus with respect to a next generation broadcast service according to another embodiment of the present invention.

FIG. 58 illustrates possible configurations of a time interleaver according to another embodiment of the present invention.

FIG. 59 illustrates a cell grouping process according to an embodiment of the present invention.

FIG. 60 illustrates a cell grouping scheme according to a modulation order according to an embodiment of the present invention.

FIG. 61 illustrates an operation of the block interleaver using cell grouping according to an embodiment of the present invention.

FIG. 62 illustrates possible configurations of a time deinterleaver according to another embodiment of the present invention.

FIG. 63 shows a mathematical expression of an operation of the block deinterleaver using cell grouping according to an embodiment of the present invention.

FIG. 64 illustrates a configuration of layered division multiplexing (LDM) according to an embodiment of the present invention.

FIG. 65 illustrates a configuration of LDM on the receiving side according to an embodiment of the present invention.

FIG. 66 illustrates the convolutional interleaver in S-PLP according to an embodiment of the present invention.

FIG. 67 illustrates signaling information for the convolutional interleaver in S-PLP according to an embodiment of the present invention.

FIG. 68 illustrates a method of transmitting a broadcast signal according to an embodiment of the present invention.

FIG. 69 illustrates a broadcast signal transmission apparatus according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The detailed description, which will be given below with reference to the accompanying drawings, is intended to explain exemplary embodiments of the present invention, rather than to show the only embodiments that can be implemented according to the present invention. The following detailed description includes specific details in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without such specific details.

Although most terms used in the present invention have been selected from general ones widely used in the art, some terms have been arbitrarily selected by the applicant and their meanings are explained in detail in the following description as needed. Thus, the present invention should be understood based upon the intended meanings of the terms rather than their simple names or meanings.

The present invention provides apparatuses and methods for transmitting and receiving broadcast signals for future broadcast services. Future broadcast services according to an embodiment of the present invention include a terrestrial broadcast service, a mobile broadcast service, a UHDTV service, etc. The present invention may process broadcast signals for the future broadcast services through non-MIMO (Multiple Input Multiple Output) or MIMO according to one embodiment. A non-MIMO scheme according to an embodiment of the present invention may include a MISO (Multiple Input Single Output) scheme, a SISO (Single Input Single Output) scheme, etc.

While MISO or MIMO uses two antennas in the following for convenience of description, the present invention is applicable to systems using two or more antennas.

The present invention may defines three physical layer (PL) profiles (base, handheld and advanced profiles), each optimized to minimize receiver complexity while attaining the performance required for a particular use case. The physical layer (PHY) profiles are subsets of all configurations that a corresponding receiver should implement.

The three PHY profiles share most of the functional blocks but differ slightly in specific blocks and/or parameters. Additional PHY profiles can be defined in the future. For the system evolution, future profiles can also be multiplexed with the existing profiles in a single RF channel through a future extension frame (FEF). The details of each PHY profile are described below.

1. Base Profile

The base profile represents a main use case for fixed receiving devices that are usually connected to a roof-top antenna. The base profile also includes portable devices that could be transported to a place but belong to a relatively stationary reception category. Use of the base profile could be extended to handheld devices or even vehicular by some improved implementations, but those use cases are not expected for the base profile receiver operation.

Target SNR range of reception is from approximately 10 to 20 dB, which includes the 15 dB SNR reception capability of the existing broadcast system (e.g. ATSC A/53). The receiver complexity and power consumption is not as critical as in the battery-operated handheld devices, which will use the handheld profile. Key system parameters for the base profile are listed in below table 1.

TABLE 1 LDPC codeword length 16K, 64K bits Constellation size 4~10 bpcu (bits per channel use) Time de-interleaving memory size ≦2¹⁹ data cells Pilot patterns Pilot pattern for fixed reception FFT size 16K, 32K points

2. Handheld Profile

The handheld profile is designed for use in handheld and vehicular devices that operate with battery power. The devices can be moving with pedestrian or vehicle speed. The power consumption as well as the receiver complexity is very important for the implementation of the devices of the handheld profile. The target SNR range of the handheld profile is approximately 0 to 10 dB, but can be configured to reach below 0 dB when intended for deeper indoor reception.

In addition to low SNR capability, resilience to the Doppler Effect caused by receiver mobility is the most important performance attribute of the handheld profile. Key system parameters for the handheld profile are listed in the below table 2.

TABLE 2 LDPC codeword length 16K bits Constellation size 2~8 bpcu Time de-interleaving memory size ≦2¹⁸ data cells Pilot patterns Pilot patterns for mobile and indoor reception FFT size 8K, 16K points

3. Advanced Profile

The advanced profile provides highest channel capacity at the cost of more implementation complexity. This profile requires using MIMO transmission and reception, and UHDTV service is a target use case for which this profile is specifically designed. The increased capacity can also be used to allow an increased number of services in a given bandwidth, e.g., multiple SDTV or HDTV services.

The target SNR range of the advanced profile is approximately 20 to 30 dB. MIMO transmission may initially use existing elliptically-polarized transmission equipment, with extension to full-power cross-polarized transmission in the future. Key system parameters for the advanced profile are listed in below table 3.

TABLE 3 LDPC codeword length 16K, 64K bits Constellation size 8~12 bpcu Time de-interleaving memory size ≦2¹⁹ data cells Pilot patterns Pilot pattern for fixed reception FFT size 16K, 32K points

In this case, the base profile can be used as a profile for both the terrestrial broadcast service and the mobile broadcast service. That is, the base profile can be used to define a concept of a profile which includes the mobile profile. Also, the advanced profile can be divided advanced profile for a base profile with MIMO and advanced profile for a handheld profile with MIMO. Moreover, the three profiles can be changed according to intention of the designer.

The following terms and definitions may apply to the present invention. The following terms and definitions can be changed according to design.

auxiliary stream: sequence of cells carrying data of as yet undefined modulation and coding, which may be used for future extensions or as required by broadcasters or network operators

base data pipe: data pipe that carries service signaling data

baseband frame (or BBFRAME): set of K_(bch) bits which form the input to one FEC encoding process (BCH and LDPC encoding)

cell: modulation value that is carried by one carrier of the OFDM transmission

coded block: LDPC-encoded block of PLS1 data or one of the LDPC-encoded blocks of PLS2 data

data pipe: logical channel in the physical layer that carries service data or related metadata, which may carry one or multiple service(s) or service component(s).

data pipe unit: a basic unit for allocating data cells to a DP in a frame.

data symbol: OFDM symbol in a frame which is not a preamble symbol (the frame signaling symbol and frame edge symbol is included in the data symbol)

DP_ID: this 8-bit field identifies uniquely a DP within the system identified by the SYSTEM_ID

dummy cell: cell carrying a pseudo-random value used to fill the remaining capacity not used for PLS signaling, DPs or auxiliary streams

emergency alert channel: part of a frame that carries EAS information data

frame: physical layer time slot that starts with a preamble and ends with a frame edge symbol

frame repetition unit: a set of frames belonging to same or different physical layer profile including a FEF, which is repeated eight times in a super-frame

fast information channel: a logical channel in a frame that carries the mapping information between a service and the corresponding base DP

FECBLOCK: set of LDPC-encoded bits of a DP data

FFT size: nominal FFT size used for a particular mode, equal to the active symbol period T_(S) expressed in cycles of the elementary period T

frame signaling symbol: OFDM symbol with higher pilot density used at the start of a frame in certain combinations of FFT size, guard interval and scattered pilot pattern, which carries a part of the PLS data

frame edge symbol: OFDM symbol with higher pilot density used at the end of a frame in certain combinations of FFT size, guard interval and scattered pilot pattern

frame-group: the set of all the frames having the same PHY profile type in a super-frame.

future extension frame: physical layer time slot within the super-frame that could be used for future extension, which starts with a preamble

Futurecast UTB system: proposed physical layer broadcasting system, of which the input is one or more MPEG2-TS or IP or general stream(s) and of which the output is an RF signal

input stream: A stream of data for an ensemble of services delivered to the end users by the system.

normal data symbol: data symbol excluding the frame signaling symbol and the frame edge symbol

PHY profile: subset of all configurations that a corresponding receiver should implement

PLS: physical layer signaling data consisting of PLS1 and PLS2

PLS1: a first set of PLS data carried in the FSS symbols having a fixed size, coding and modulation, which carries basic information about the system as well as the parameters needed to decode the PLS2

NOTE: PLS1 data remains constant for the duration of a frame-group.

PLS2: a second set of PLS data transmitted in the FSS symbol, which carries more detailed PLS data about the system and the DPs

PLS2 dynamic data: PLS2 data that may dynamically change frame-by-frame

PLS2 static data: PLS2 data that remains static for the duration of a frame-group

preamble signaling data: signaling data carried by the preamble symbol and used to identify the basic mode of the system

preamble symbol: fixed-length pilot symbol that carries basic PLS data and is located in the beginning of a frame

NOTE: The preamble symbol is mainly used for fast initial band scan to detect the system signal, its timing, frequency offset, and FFT-size.

reserved for future use: not defined by the present document but may be defined in future

super-frame: set of eight frame repetition units

time interleaving block (TI block): set of cells within which time interleaving is carried out, corresponding to one use of the time interleaver memory

TI group: unit over which dynamic capacity allocation for a particular DP is carried out, made up of an integer, dynamically varying number of XFECBLOCKs.

NOTE: The TI group may be mapped directly to one frame or may be mapped to multiple frames. It may contain one or more TI blocks.

Type 1 DP: DP of a frame where all DPs are mapped into the frame in TDM fashion

Type 2 DP: DP of a frame where all DPs are mapped into the frame in FDM fashion

XFECBLOCK: set of N_(cells) cells carrying all the bits of one LDPC FECBLOCK

FIG. 1 illustrates a structure of an apparatus for transmitting broadcast signals for future broadcast services according to an embodiment of the present invention.

The apparatus for transmitting broadcast signals for future broadcast services according to an embodiment of the present invention can include an input formatting block 1000, a BICM (Bit interleaved coding & modulation) block 1010, a frame structure block 1020, an OFDM (Orthogonal Frequency Division Multiplexing) generation block 1030 and a signaling generation block 1040. A description will be given of the operation of each module of the apparatus for transmitting broadcast signals.

IP stream/packets and MPEG2-TS are the main input formats, other stream types are handled as General Streams. In addition to these data inputs, Management Information is input to control the scheduling and allocation of the corresponding bandwidth for each input stream. One or multiple TS stream(s), IP stream(s) and/or General Stream(s) inputs are simultaneously allowed.

The input formatting block 1000 can demultiplex each input stream into one or multiple data pipe(s), to each of which an independent coding and modulation is applied. The data pipe (DP) is the basic unit for robustness control, thereby affecting quality-of-service (QoS). One or multiple service(s) or service component(s) can be carried by a single DP. Details of operations of the input formatting block 1000 will be described later.

The data pipe is a logical channel in the physical layer that carries service data or related metadata, which may carry one or multiple service(s) or service component(s).

Also, the data pipe unit: a basic unit for allocating data cells to a DP in a frame.

In the BICM block 1010, parity data is added for error correction and the encoded bit streams are mapped to complex-value constellation symbols. The symbols are interleaved across a specific interleaving depth that is used for the corresponding DP. For the advanced profile, MIMO encoding is performed in the BICM block 1010 and the additional data path is added at the output for MIMO transmission. Details of operations of the BICM block 1010 will be described later.

The Frame Building block 1020 can map the data cells of the input DPs into the OFDM symbols within a frame. After mapping, the frequency interleaving is used for frequency-domain diversity, especially to combat frequency-selective fading channels. Details of operations of the Frame Building block 1020 will be described later.

After inserting a preamble at the beginning of each frame, the OFDM Generation block 1030 can apply conventional OFDM modulation having a cyclic prefix as guard interval. For antenna space diversity, a distributed MISO scheme is applied across the transmitters. In addition, a Peak-to-Average Power Reduction (PAPR) scheme is performed in the time domain. For flexible network planning, this proposal provides a set of various FFT sizes, guard interval lengths and corresponding pilot patterns. Details of operations of the OFDM Generation block 1030 will be described later.

The Signaling Generation block 1040 can create physical layer signaling information used for the operation of each functional block. This signaling information is also transmitted so that the services of interest are properly recovered at the receiver side. Details of operations of the Signaling Generation block 1040 will be described later.

FIGS. 2, 3 and 4 illustrate the input formatting block 1000 according to embodiments of the present invention. A description will be given of each figure.

FIG. 2 illustrates an input formatting block according to one embodiment of the present invention. FIG. 2 shows an input formatting module when the input signal is a single input stream.

The input formatting block illustrated in FIG. 2 corresponds to an embodiment of the input formatting block 1000 described with reference to FIG. 1.

The input to the physical layer may be composed of one or multiple data streams. Each data stream is carried by one DP. The mode adaptation modules slice the incoming data stream into data fields of the baseband frame (BBF). The system supports three types of input data streams: MPEG2-TS, Internet protocol (IP) and Generic stream (GS). MPEG2-TS is characterized by fixed length (188 byte) packets with the first byte being a sync-byte (0x47). An IP stream is composed of variable length IP datagram packets, as signaled within IP packet headers. The system supports both IPv4 and IPv6 for the IP stream. GS may be composed of variable length packets or constant length packets, signaled within encapsulation packet headers.

(a) shows a mode adaptation block 2000 and a stream adaptation 2010 for signal DP and (b) shows a PLS generation block 2020 and a PLS scrambler 2030 for generating and processing PLS data. A description will be given of the operation of each block.

The Input Stream Splitter splits the input TS, IP, GS streams into multiple service or service component (audio, video, etc.) streams. The mode adaptation module 2010 is comprised of a CRC Encoder, BB (baseband) Frame Slicer, and BB Frame Header Insertion block.

The CRC Encoder provides three kinds of CRC encoding for error detection at the user packet (UP) level, i.e., CRC-8, CRC-16, and CRC-32. The computed CRC bytes are appended after the UP. CRC-8 is used for TS stream and CRC-32 for IP stream. If the GS stream doesn't provide the CRC encoding, the proposed CRC encoding should be applied.

BB Frame Slicer maps the input into an internal logical-bit format. The first received bit is defined to be the MSB. The BB Frame Slicer allocates a number of input bits equal to the available data field capacity. To allocate a number of input bits equal to the BBF payload, the UP packet stream is sliced to fit the data field of BBF.

BB Frame Header Insertion block can insert fixed length BBF header of 2 bytes is inserted in front of the BB Frame. The BBF header is composed of STUFFI (1 bit), SYNCD (13 bits), and RFU (2 bits). In addition to the fixed 2-Byte BBF header, BBF can have an extension field (1 or 3 bytes) at the end of the 2-byte BBF header.

The stream adaptation 2010 is comprised of stuffing insertion block and BB scrambler.

The stuffing insertion block can insert stuffing field into a payload of a BB frame. If the input data to the stream adaptation is sufficient to fill a BB-Frame, STUFFI is set to ‘0’ and the BBF has no stuffing field. Otherwise STUFFI is set to ‘1’ and the stuffing field is inserted immediately after the BBF header. The stuffing field comprises two bytes of the stuffing field header and a variable size of stuffing data.

The BB scrambler scrambles complete BBF for energy dispersal. The scrambling sequence is synchronous with the BBF. The scrambling sequence is generated by the feed-back shift register.

The PLS generation block 2020 can generate physical layer signaling (PLS) data. The PLS provides the receiver with a means to access physical layer DPs. The PLS data consists of PLS1 data and PLS2 data.

The PLS1 data is a first set of PLS data carried in the FSS symbols in the frame having a fixed size, coding and modulation, which carries basic information about the system as well as the parameters needed to decode the PLS2 data. The PLS1 data provides basic transmission parameters including parameters required to enable the reception and decoding of the PLS2 data. Also, the PLS1 data remains constant for the duration of a frame-group.

The PLS2 data is a second set of PLS data transmitted in the FSS symbol, which carries more detailed PLS data about the system and the DPs. The PLS2 contains parameters that provide sufficient information for the receiver to decode the desired DP. The PLS2 signaling further consists of two types of parameters, PLS2 Static data (PLS2-STAT data) and PLS2 dynamic data (PLS2-DYN data). The PLS2 Static data is PLS2 data that remains static for the duration of a frame-group and the PLS2 dynamic data is PLS2 data that may dynamically change frame-by-frame.

Details of the PLS data will be described later.

The PLS scrambler 2030 can scramble the generated PLS data for energy dispersal.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions.

FIG. 3 illustrates an input formatting block according to another embodiment of the present invention.

The input formatting block illustrated in FIG. 3 corresponds to an embodiment of the input formatting block 1000 described with reference to FIG. 1.

FIG. 3 shows a mode adaptation block of the input formatting block when the input signal corresponds to multiple input streams.

The mode adaptation block of the input formatting block for processing the multiple input streams can independently process the multiple input streams.

Referring to FIG. 3, the mode adaptation block for respectively processing the multiple input streams can include an input stream splitter 3000, an input stream synchronizer 3010, a compensating delay block 3020, a null packet deletion block 3030, a head compression block 3040, a CRC encoder 3050, a BB frame slicer 3060 and a BB header insertion block 3070. Description will be given of each block of the mode adaptation block.

Operations of the CRC encoder 3050, BB frame slicer 3060 and BB header insertion block 3070 correspond to those of the CRC encoder, BB frame slicer and BB header insertion block described with reference to FIG. 2 and thus description thereof is omitted.

The input stream splitter 3000 can split the input TS, IP, GS streams into multiple service or service component (audio, video, etc.) streams.

The input stream synchronizer 3010 may be referred as ISSY. The ISSY can provide suitable means to guarantee Constant Bit Rate (CBR) and constant end-to-end transmission delay for any input data format. The ISSY is always used for the case of multiple DPs carrying TS, and optionally used for multiple DPs carrying GS streams.

The compensating delay block 3020 can delay the split TS packet stream following the insertion of ISSY information to allow a TS packet recombining mechanism without requiring additional memory in the receiver.

The null packet deletion block 3030, is used only for the TS input stream case. Some TS input streams or split TS streams may have a large number of null-packets present in order to accommodate VBR (variable bit-rate) services in a CBR TS stream. In this case, in order to avoid unnecessary transmission overhead, null-packets can be identified and not transmitted. In the receiver, removed null-packets can be re-inserted in the exact place where they were originally by reference to a deleted null-packet (DNP) counter that is inserted in the transmission, thus guaranteeing constant bit-rate and avoiding the need for time-stamp (PCR) updating.

The head compression block 3040 can provide packet header compression to increase transmission efficiency for TS or IP input streams. Because the receiver can have a priori information on certain parts of the header, this known information can be deleted in the transmitter.

For Transport Stream, the receiver has a-priori information about the sync-byte configuration (0x47) and the packet length (188 Byte). If the input TS stream carries content that has only one PID, i.e., for only one service component (video, audio, etc.) or service sub-component (SVC base layer, SVC enhancement layer, MVC base view or MVC dependent views), TS packet header compression can be applied (optionally) to the Transport Stream. IP packet header compression is used optionally if the input steam is an IP stream.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions.

FIG. 4 illustrates an input formatting block according to another embodiment of the present invention.

The input formatting block illustrated in FIG. 4 corresponds to an embodiment of the input formatting block 1000 described with reference to FIG. 1.

FIG. 4 illustrates a stream adaptation block of the input formatting module when the input signal corresponds to multiple input streams.

Referring to FIG. 4, the mode adaptation block for respectively processing the multiple input streams can include a scheduler 4000, an 1-Frame delay block 4010, a stuffing insertion block 4020, an in-band signaling 4030, a BB Frame scrambler 4040, a PLS generation block 4050 and a PLS scrambler 4060. Description will be given of each block of the stream adaptation block.

Operations of the stuffing insertion block 4020, the BB Frame scrambler 4040, the PLS generation block 4050 and the PLS scrambler 4060 correspond to those of the stuffing insertion block, BB scrambler, PLS generation block and the PLS scrambler described with reference to FIG. 2 and thus description thereof is omitted.

The scheduler 4000 can determine the overall cell allocation across the entire frame from the amount of FECBLOCKs of each DP. Including the allocation for PLS, EAC and FIC, the scheduler generate the values of PLS2-DYN data, which is transmitted as in-band signaling or PLS cell in FSS of the frame. Details of FECBLOCK, EAC and FIC will be described later.

The 1-Frame delay block 4010 can delay the input data by one transmission frame such that scheduling information about the next frame can be transmitted through the current frame for in-band signaling information to be inserted into the DPs.

The in-band signaling 4030 can insert un-delayed part of the PLS2 data into a DP of a frame.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions.

FIG. 5 illustrates a BICM block according to an embodiment of the present invention.

The BICM block illustrated in FIG. 5 corresponds to an embodiment of the BICM block 1010 described with reference to FIG. 1.

As described above, the apparatus for transmitting broadcast signals for future broadcast services according to an embodiment of the present invention can provide a terrestrial broadcast service, mobile broadcast service, UHDTV service, etc.

Since QoS (quality of service) depends on characteristics of a service provided by the apparatus for transmitting broadcast signals for future broadcast services according to an embodiment of the present invention, data corresponding to respective services needs to be processed through different schemes. Accordingly, the a BICM block according to an embodiment of the present invention can independently process DPs input thereto by independently applying SISO, MISO and MIMO schemes to the data pipes respectively corresponding to data paths. Consequently, the apparatus for transmitting broadcast signals for future broadcast services according to an embodiment of the present invention can control QoS for each service or service component transmitted through each DP.

(a) shows the BICM block shared by the base profile and the handheld profile and (b) shows the BICM block of the advanced profile.

The BICM block shared by the base profile and the handheld profile and the BICM block of the advanced profile can include plural processing blocks for processing each DP.

A description will be given of each processing block of the BICM block for the base profile and the handheld profile and the BICM block for the advanced profile.

A processing block 5000 of the BICM block for the base profile and the handheld profile can include a Data FEC encoder 5010, a bit interleaver 5020, a constellation mapper 5030, an SSD (Signal Space Diversity) encoding block 5040 and a time interleaver 5050.

The Data FEC encoder 5010 can perform the FEC encoding on the input BBF to generate FECBLOCK procedure using outer coding (BCH), and inner coding (LDPC). The outer coding (BCH) is optional coding method. Details of operations of the Data FEC encoder 5010 will be described later.

The bit interleaver 5020 can interleave outputs of the Data FEC encoder 5010 to achieve optimized performance with combination of the LDPC codes and modulation scheme while providing an efficiently implementable structure. Details of operations of the bit interleaver 5020 will be described later.

The constellation mapper 5030 can modulate each cell word from the bit interleaver 5020 in the base and the handheld profiles, or cell word from the Cell-word demultiplexer 5010-1 in the advanced profile using either QPSK, QAM-16, non-uniform QAM (NUQ-64, NUQ-256, NUQ-1024) or non-uniform constellation (NUC-16, NUC-64, NUC-256, NUC-1024) to give a power-normalized constellation point, e_(l). This constellation mapping is applied only for DPs. Observe that QAM-16 and NUQs are square shaped, while NUCs have arbitrary shape. When each constellation is rotated by any multiple of 90 degrees, the rotated constellation exactly overlaps with its original one. This “rotation-sense” symmetric property makes the capacities and the average powers of the real and imaginary components equal to each other. Both NUQs and NUCs are defined specifically for each code rate and the particular one used is signaled by the parameter DP_MOD filed in PLS2 data.

The SSD encoding block 5040 can precode cells in two (2D), three (3D), and four (4D) dimensions to increase the reception robustness under difficult fading conditions.

The time interleaver 5050 can operates at the DP level. The parameters of time interleaving (TI) may be set differently for each DP. Details of operations of the time interleaver 5050 will be described later.

A processing block 5000-1 of the BICM block for the advanced profile can include the Data FEC encoder, bit interleaver, constellation mapper, and time interleaver. However, the processing block 5000-1 is distinguished from the processing block 5000 further includes a cell-word demultiplexer 5010-1 and a MIMO encoding block 5020-1.

Also, the operations of the Data FEC encoder, bit interleaver, constellation mapper, and time interleaver in the processing block 5000-1 correspond to those of the Data FEC encoder 5010, bit interleaver 5020, constellation mapper 5030, and time interleaver 5050 described and thus description thereof is omitted.

The cell-word demultiplexer 5010-1 is used for the DP of the advanced profile to divide the single cell-word stream into dual cell-word streams for MIMO processing. Details of operations of the cell-word demultiplexer 5010-1 will be described later.

The MIMO encoding block 5020-1 can processing the output of the cell-word demultiplexer 5010-1 using MIMO encoding scheme. The MIMO encoding scheme was optimized for broadcasting signal transmission. The MIMO technology is a promising way to get a capacity increase but it depends on channel characteristics. Especially for broadcasting, the strong LOS component of the channel or a difference in the received signal power between two antennas caused by different signal propagation characteristics makes it difficult to get capacity gain from MIMO. The proposed MIMO encoding scheme overcomes this problem using a rotation-based pre-coding and phase randomization of one of the MIMO output signals.

MIMO encoding is intended for a 2×2 MIMO system requiring at least two antennas at both the transmitter and the receiver. Two MIMO encoding modes are defined in this proposal; full-rate spatial multiplexing (FR-SM) and full-rate full-diversity spatial multiplexing (FRFD-SM). The FR-SM encoding provides capacity increase with relatively small complexity increase at the receiver side while the FRFD-SM encoding provides capacity increase and additional diversity gain with a great complexity increase at the receiver side. The proposed MIMO encoding scheme has no restriction on the antenna polarity configuration.

MIMO processing is required for the advanced profile frame, which means all DPs in the advanced profile frame are processed by the MIMO encoder. MIMO processing is applied at DP level. Pairs of the Constellation Mapper outputs NUQ (e_(1,i) and e_(2,i)) are fed to the input of the MIMO Encoder. Paired MIMO Encoder output (g1,i and g2,i) is transmitted by the same carrier k and OFDM symbol 1 of their respective TX antennas.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions.

FIG. 6 illustrates a BICM block according to another embodiment of the present invention.

The BICM block illustrated in FIG. 6 corresponds to an embodiment of the BICM block 1010 described with reference to FIG. 1.

FIG. 6 illustrates a BICM block for protection of physical layer signaling (PLS), emergency alert channel (EAC) and fast information channel (FIC). EAC is a part of a frame that carries EAS information data and FIC is a logical channel in a frame that carries the mapping information between a service and the corresponding base DP. Details of the EAC and FIC will be described later.

Referring to FIG. 6, the BICM block for protection of PLS, EAC and FIC can include a PLS FEC encoder 6000, a bit interleaver 6010, and a constellation mapper 6020.

Also, the PLS FEC encoder 6000 can include a scrambler, BCH encoding/zero insertion block, LDPC encoding block and LDPC parity punturing block. Description will be given of each block of the BICM block.

The PLS FEC encoder 6000 can encode the scrambled PLS 1/2 data, EAC and FIC section.

The scrambler can scramble PLS1 data and PLS2 data before BCH encoding and shortened and punctured LDPC encoding.

The BCH encoding/zero insertion block can perform outer encoding on the scrambled PLS 1/2 data using the shortened BCH code for PLS protection and insert zero bits after the BCH encoding. For PLS1 data only, the output bits of the zero insertion may be permutted before LDPC encoding.

The LDPC encoding block can encode the output of the BCH encoding/zero insertion block using LDPC code. To generate a complete coded block, C_(ldpc), parity bits, P_(ldpc) are encoded systematically from each zero-inserted PLS information block, L_(ldpc) and appended after it.

C _(ldpc) =[I _(ldpc) P _(ldpc) ]=[i ₀ ,i ₁ , . . . ,i _(K) _(ldpc) ⁻¹ ,p ₀ ,p ₁ , . . . ,p _(N) _(ldpc) _(−K) _(ldpc) ⁻¹]  [Expression 1]

The LDPC code parameters for PLS1 and PLS2 are as following table 4.

TABLE 4 Signaling K_(ldpc) code Type K_(sig) K_(bch) N_(bch) _(—) _(parity) (=N_(bch)) N_(ldpc) N_(ldpc) _(—) _(parity) rate Q_(ldpc) PLS1 342 1020 60 1080 4320 3240 1/4  36 PLS2 <1021 >1020 2100 2160 7200 5040 3/10 56

The LDPC parity punturing block can perform puncturing on the PLS1 data and PLS 2 data.

When shortening is applied to the PLS1 data protection, some LDPC parity bits are punctured after LDPC encoding. Also, for the PLS2 data protection, the LDPC parity bits of PLS2 are punctured after LDPC encoding. These punctured bits are not transmitted.

The bit interleaver 6010 can interleave the each shortened and punctured PLS1 data and PLS2 data.

The constellation mapper 6020 can map the bit ineterlaeved PLS1 data and PLS2 data onto constellations.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions.

FIG. 7 illustrates a frame building block according to one embodiment of the present invention.

The frame building block illustrated in FIG. 7 corresponds to an embodiment of the frame building block 1020 described with reference to FIG. 1.

Referring to FIG. 7, the frame building block can include a delay compensation block 7000, a cell mapper 7010 and a frequency interleaver 7020. Description will be given of each block of the frame building block.

The delay compensation block 7000 can adjust the timing between the data pipes and the corresponding PLS data to ensure that they are co-timed at the transmitter end. The PLS data is delayed by the same amount as data pipes are by addressing the delays of data pipes caused by the Input Formatting block and BICM block. The delay of the BICM block is mainly due to the time interleaver. In-band signaling data carries information of the next TI group so that they are carried one frame ahead of the DPs to be signaled. The Delay Compensating block delays in-band signaling data accordingly.

The cell mapper 7010 can map PLS, EAC, FIC, DPs, auxiliary streams and dummy cells into the active carriers of the OFDM symbols in the frame. The basic function of the cell mapper 7010 is to map data cells produced by the TIs for each of the DPs, PLS cells, and EAC/FIC cells, if any, into arrays of active OFDM cells corresponding to each of the OFDM symbols within a frame. Service signaling data (such as PSI (program specific information)/SI) can be separately gathered and sent by a data pipe. The Cell Mapper operates according to the dynamic information produced by the scheduler and the configuration of the frame structure. Details of the frame will be described later.

The frequency interleaver 7020 can randomly interleave data cells received from the cell mapper 7010 to provide frequency diversity. Also, the frequency interleaver 7020 can operate on very OFDM symbol pair comprised of two sequential OFDM symbols using a different interleaving-seed order to get maximum interleaving gain in a single frame.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions.

FIG. 8 illustrates an OFDM generation block according to an embodiment of the present invention.

The OFDM generation block illustrated in FIG. 8 corresponds to an embodiment of the OFDM generation block 1030 described with reference to FIG. 1.

The OFDM generation block modulates the OFDM carriers by the cells produced by the Frame Building block, inserts the pilots, and produces the time domain signal for transmission. Also, this block subsequently inserts guard intervals, and applies PAPR (Peak-to-Average Power Radio) reduction processing to produce the final RF signal.

Referring to FIG. 8, the frame building block can include a pilot and reserved tone insertion block 8000, a 2D-eSFN encoding block 8010, an IFFT (Inverse Fast Fourier Transform) block 8020, a PAPR reduction block 8030, a guard interval insertion block 8040, a preamble insertion block 8050, other system insertion block 8060 and a DAC block 8070. Description will be given of each block of the frame building block.

The pilot and reserved tone insertion block 8000 can insert pilots and the reserved tone.

Various cells within the OFDM symbol are modulated with reference information, known as pilots, which have transmitted values known a priori in the receiver. The information of pilot cells is made up of scattered pilots, continual pilots, edge pilots, FSS (frame signaling symbol) pilots and FES (frame edge symbol) pilots. Each pilot is transmitted at a particular boosted power level according to pilot type and pilot pattern. The value of the pilot information is derived from a reference sequence, which is a series of values, one for each transmitted carrier on any given symbol. The pilots can be used for frame synchronization, frequency synchronization, time synchronization, channel estimation, and transmission mode identification, and also can be used to follow the phase noise.

Reference information, taken from the reference sequence, is transmitted in scattered pilot cells in every symbol except the preamble, FSS and FES of the frame. Continual pilots are inserted in every symbol of the frame. The number and location of continual pilots depends on both the FFT size and the scattered pilot pattern. The edge carriers are edge pilots in every symbol except for the preamble symbol. They are inserted in order to allow frequency interpolation up to the edge of the spectrum. FSS pilots are inserted in FSS(s) and FES pilots are inserted in FES. They are inserted in order to allow time interpolation up to the edge of the frame.

The system according to an embodiment of the present invention supports the SFN network, where distributed MISO scheme is optionally used to support very robust transmission mode. The 2D-eSFN is a distributed MISO scheme that uses multiple TX antennas, each of which is located in the different transmitter site in the SFN network.

The 2D-eSFN encoding block 8010 can process a 2D-eSFN processing to distorts the phase of the signals transmitted from multiple transmitters, in order to create both time and frequency diversity in the SFN configuration. Hence, burst errors due to low flat fading or deep-fading for a long time can be mitigated.

The IFFT block 8020 can modulate the output from the 2D-eSFN encoding block 8010 using OFDM modulation scheme. Any cell in the data symbols which has not been designated as a pilot (or as a reserved tone) carries one of the data cells from the frequency interleaver. The cells are mapped to OFDM carriers.

The PAPR reduction block 8030 can perform a PAPR reduction on input signal using various PAPR reduction algorithm in the time domain.

The guard interval insertion block 8040 can insert guard intervals and the preamble insertion block 8050 can insert preamble in front of the signal. Details of a structure of the preamble will be described later. The other system insertion block 8060 can multiplex signals of a plurality of broadcast transmission/reception systems in the time domain such that data of two or more different broadcast transmission/reception systems providing broadcast services can be simultaneously transmitted in the same RF signal bandwidth. In this case, the two or more different broadcast transmission/reception systems refer to systems providing different broadcast services. The different broadcast services may refer to a terrestrial broadcast service, mobile broadcast service, etc. Data related to respective broadcast services can be transmitted through different frames.

The DAC block 8070 can convert an input digital signal into an analog signal and output the analog signal. The signal output from the DAC block 7800 can be transmitted through multiple output antennas according to the physical layer profiles. A Tx antenna according to an embodiment of the present invention can have vertical or horizontal polarity.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions according to design.

FIG. 9 illustrates a structure of an apparatus for receiving broadcast signals for future broadcast services according to an embodiment of the present invention.

The apparatus for receiving broadcast signals for future broadcast services according to an embodiment of the present invention can correspond to the apparatus for transmitting broadcast signals for future broadcast services, described with reference to FIG. 1.

The apparatus for receiving broadcast signals for future broadcast services according to an embodiment of the present invention can include a synchronization & demodulation module 9000, a frame parsing module 9010, a demapping & decoding module 9020, an output processor 9030 and a signaling decoding module 9040. A description will be given of operation of each module of the apparatus for receiving broadcast signals.

The synchronization & demodulation module 9000 can receive input signals through m Rx antennas, perform signal detection and synchronization with respect to a system corresponding to the apparatus for receiving broadcast signals and carry out demodulation corresponding to a reverse procedure of the procedure performed by the apparatus for transmitting broadcast signals.

The frame parsing module 9100 can parse input signal frames and extract data through which a service selected by a user is transmitted. If the apparatus for transmitting broadcast signals performs interleaving, the frame parsing module 9100 can carry out deinterleaving corresponding to a reverse procedure of interleaving. In this case, the positions of a signal and data that need to be extracted can be obtained by decoding data output from the signaling decoding module 9400 to restore scheduling information generated by the apparatus for transmitting broadcast signals.

The demapping & decoding module 9200 can convert the input signals into bit domain data and then deinterleave the same as necessary. The demapping & decoding module 9200 can perform demapping for mapping applied for transmission efficiency and correct an error generated on a transmission channel through decoding. In this case, the demapping & decoding module 9200 can obtain transmission parameters necessary for demapping and decoding by decoding the data output from the signaling decoding module 9400.

The output processor 9300 can perform reverse procedures of various compression/signal processing procedures which are applied by the apparatus for transmitting broadcast signals to improve transmission efficiency. In this case, the output processor 9300 can acquire necessary control information from data output from the signaling decoding module 9400. The output of the output processor 8300 corresponds to a signal input to the apparatus for transmitting broadcast signals and may be MPEG-TSs, IP streams (v4 or v6) and generic streams.

The signaling decoding module 9400 can obtain PLS information from the signal demodulated by the synchronization & demodulation module 9000. As described above, the frame parsing module 9100, demapping & decoding module 9200 and output processor 9300 can execute functions thereof using the data output from the signaling decoding module 9400.

FIG. 10 illustrates a frame structure according to an embodiment of the present invention.

FIG. 10 shows an example configuration of the frame types and FRUs in a super-frame. (a) shows a super frame according to an embodiment of the present invention, (b) shows FRU (Frame Repetition Unit) according to an embodiment of the present invention, (c) shows frames of variable PHY profiles in the FRU and (d) shows a structure of a frame.

A super-frame may be composed of eight FRUs. The FRU is a basic multiplexing unit for TDM of the frames, and is repeated eight times in a super-frame.

Each frame in the FRU belongs to one of the PHY profiles, (base, handheld, advanced) or FEF. The maximum allowed number of the frames in the FRU is four and a given PHY profile can appear any number of times from zero times to four times in the FRU (e.g., base, base, handheld, advanced). PHY profile definitions can be extended using reserved values of the PHY_PROFILE in the preamble, if required.

The FEF part is inserted at the end of the FRU, if included. When the FEF is included in the FRU, the minimum number of FEFs is 8 in a super-frame. It is not recommended that FEF parts be adjacent to each other.

One frame is further divided into a number of OFDM symbols and a preamble. As shown in (d), the frame comprises a preamble, one or more frame signaling symbols (FSS), normal data symbols and a frame edge symbol (FES).

The preamble is a special symbol that enables fast Futurecast UTB system signal detection and provides a set of basic transmission parameters for efficient transmission and reception of the signal. The detailed description of the preamble will be will be described later.

The main purpose of the FSS(s) is to carry the PLS data. For fast synchronization and channel estimation, and hence fast decoding of PLS data, the FSS has more dense pilot pattern than the normal data symbol. The FES has exactly the same pilots as the FSS, which enables frequency-only interpolation within the FES and temporal interpolation, without extrapolation, for symbols immediately preceding the FES.

FIG. 11 illustrates a signaling hierarchy structure of the frame according to an embodiment of the present invention.

FIG. 11 illustrates the signaling hierarchy structure, which is split into three main parts: the preamble signaling data 11000, the PLS1 data 11010 and the PLS2 data 11020. The purpose of the preamble, which is carried by the preamble symbol in every frame, is to indicate the transmission type and basic transmission parameters of that frame. The PLS1 enables the receiver to access and decode the PLS2 data, which contains the parameters to access the DP of interest. The PLS2 is carried in every frame and split into two main parts: PLS2-STAT data and PLS2-DYN data. The static and dynamic portion of PLS2 data is followed by padding, if necessary.

FIG. 12 illustrates preamble signaling data according to an embodiment of the present invention.

Preamble signaling data carries 21 bits of information that are needed to enable the receiver to access PLS data and trace DPs within the frame structure. Details of the preamble signaling data are as follows:

PHY_PROFILE: This 3-bit field indicates the PHY profile type of the current frame. The mapping of different PHY profile types is given in below table 5.

TABLE 5 Value PHY profile 000 Base profile 001 Handheld profile 010 Advanced profiled 011~110 Reserved 111 FEF

FFT_SIZE: This 2 bit field indicates the FFT size of the current frame within a frame-group, as described in below table 6.

TABLE 6 Value FFT size 00 8K FFT 01 16K FFT 10 32K FFT 11 Reserved

GI_FRACTION: This 3 bit field indicates the guard interval fraction value in the current super-frame, as described in below table 7.

TABLE 7 Value GI_FRACTION 000 ⅕ 001 1/10 010 1/20 011 1/40 100 1/80 101 1/160 110~111 Reserved

EAC_FLAG: This 1 bit field indicates whether the EAC is provided in the current frame. If this field is set to ‘ 1’, emergency alert service (EAS) is provided in the current frame. If this field set to ‘0’, EAS is not carried in the current frame. This field can be switched dynamically within a super-frame.

PILOT_MODE: This 1-bit field indicates whether the pilot mode is mobile mode or fixed mode for the current frame in the current frame-group. If this field is set to ‘0’, mobile pilot mode is used. If the field is set to ‘1’, the fixed pilot mode is used.

PAPR_FLAG: This 1-bit field indicates whether PAPR reduction is used for the current frame in the current frame-group. If this field is set to value ‘1’, tone reservation is used for PAPR reduction. If this field is set to ‘0’, PAPR reduction is not used.

FRU_CONFIGURE: This 3-bit field indicates the PHY profile type configurations of the frame repetition units (FRU) that are present in the current super-frame. All profile types conveyed in the current super-frame are identified in this field in all preambles in the current super-frame. The 3-bit field has a different definition for each profile, as show in below table 8.

TABLE 8 Current Current Current PHY_PROFILE = PHY_PROFILE = Current PHY_PROFILE = ‘001’ ‘010’ PHY_PROFILE = ‘000’ (base) (handheld) (advanced) ‘111’ (FEF) FRU_CONFIGURE = Only base Only handheld Only advanced Only FEF 000 profile profile present profile present present present FRU_CONFIGURE = Handheld profile Base profile Base profile Base profile 1XX present present present present FRU_CONFIGURE = Advanced Advanced Handheld profile Handheld profile X1X profile profile present present present present FRU_CONFIGURE = FEF FEF FEF Advanced XX1 present present present profile present

RESERVED: This 7-bit field is reserved for future use.

FIG. 13 illustrates PLS1 data according to an embodiment of the present invention.

PLS1 data provides basic transmission parameters including parameters required to enable the reception and decoding of the PLS2. As above mentioned, the PLS1 data remain unchanged for the entire duration of one frame-group. The detailed definition of the signaling fields of the PLS1 data are as follows:

PREAMBLE_DATA: This 20-bit field is a copy of the preamble signaling data excluding the EAC_FLAG.

NUM_FRAME_FRU: This 2-bit field indicates the number of the frames per FRU.

PAYLOAD_TYPE: This 3-bit field indicates the format of the payload data carried in the frame-group. PAYLOAD_TYPE is signaled as shown in table 9.

TABLE 9 value Payload type 1XX TS stream is transmitted X1X IP stream is transmitted XX1 GS stream is transmitted

NUM_FSS: This 2-bit field indicates the number of FSS symbols in the current frame.

SYSTEM_VERSION: This 8-bit field indicates the version of the transmitted signal format. The SYSTEM_VERSION is divided into two 4-bit fields, which are a major version and a minor version.

Major version: The MSB four bits of SYSTEM_VERSION field indicate major version information. A change in the major version field indicates a non-backward-compatible change. The default value is ‘0000’. For the version described in this standard, the value is set to ‘0000’.

Minor version: The LSB four bits of SYSTEM_VERSION field indicate minor version information. A change in the minor version field is backward-compatible.

CELL_ID: This is a 16-bit field which uniquely identifies a geographic cell in an ATSC network. An ATSC cell coverage area may consist of one or more frequencies, depending on the number of frequencies used per Futurecast UTB system. If the value of the CELL_ID is not known or unspecified, this field is set to ‘0’.

NETWORK_ID: This is a 16-bit field which uniquely identifies the current ATSC network.

SYSTEM_ID: This 16-bit field uniquely identifies the Futurecast UTB system within the ATSC network. The Futurecast UTB system is the terrestrial broadcast system whose input is one or more input streams (TS, IP, GS) and whose output is an RF signal. The Futurecast UTB system carries one or more PHY profiles and FEF, if any. The same Futurecast UTB system may carry different input streams and use different RF frequencies in different geographical areas, allowing local service insertion. The frame structure and scheduling is controlled in one place and is identical for all transmissions within a Futurecast UTB system. One or more Futurecast UTB systems may have the same SYSTEM_ID meaning that they all have the same physical layer structure and configuration.

The following loop consists of FRU_PHY_PROFILE, FRU_FRAME_LENGTH, FRU_GI_FRACTION, and RESERVED which are used to indicate the FRU configuration and the length of each frame type. The loop size is fixed so that four PHY profiles (including a FEF) are signaled within the FRU. If NUM_FRAME_FRU is less than 4, the unused fields are filled with zeros.

FRU_PHY_PROFILE: This 3-bit field indicates the PHY profile type of the (i+1)^(th) (i is the loop index) frame of the associated FRU. This field uses the same signaling format as shown in the table 8.

FRU_FRAME_LENGTH: This 2-bit field indicates the length of the (i+1)^(th) frame of the associated FRU. Using FRU_FRAME_LENGTH together with FRU_GI_FRACTION, the exact value of the frame duration can be obtained.

FRU_GI_FRACTION: This 3-bit field indicates the guard interval fraction value of the (i+1)^(th) frame of the associated FRU. FRU_GI_FRACTION is signaled according to the table 7.

RESERVED: This 4-bit field is reserved for future use.

The following fields provide parameters for decoding the PLS2 data.

PLS2_FEC_TYPE: This 2-bit field indicates the FEC type used by the PLS2 protection. The FEC type is signaled according to table 10. The details of the LDPC codes will be described later.

TABLE 10 Content PLS2 FEC type 00 4K-1/4 and 7K-3/10 LDPC codes 01~11 Reserved

PLS2_MOD: This 3-bit field indicates the modulation type used by the PLS2. The modulation type is signaled according to table 11.

TABLE 11 Value PLS2_MODE 000 BPSK 001 QPSK 010 QAM-16 011 NUQ-64 100~111 Reserved

PLS2_SIZE_CELL: This 15-bit field indicates C_(total) _(_) _(partial) _(_) _(block), the size (specified as the number of QAM cells) of the collection of full coded blocks for PLS2 that is carried in the current frame-group. This value is constant during the entire duration of the current frame-group.

PLS2_STAT_SIZE_BIT: This 14-bit field indicates the size, in bits, of the PLS2-STAT for the current frame-group. This value is constant during the entire duration of the current frame-group.

PLS2_DYN_SIZE_BIT: This 14-bit field indicates the size, in bits, of the PLS2-DYN for the current frame-group. This value is constant during the entire duration of the current frame-group.

PLS2_REP_FLAG: This 1-bit flag indicates whether the PLS2 repetition mode is used in the current frame-group. When this field is set to value ‘1’, the PLS2 repetition mode is activated. When this field is set to value ‘0’, the PLS2 repetition mode is deactivated.

PLS2_REP_SIZE_CELL: This 15-bit field indicates C_(total) _(_) _(partial) _(_) _(block), the size (specified as the number of QAM cells) of the collection of partial coded blocks for PLS2 carried in every frame of the current frame-group, when PLS2 repetition is used. If repetition is not used, the value of this field is equal to 0. This value is constant during the entire duration of the current frame-group.

PLS2_NEXT_FEC_TYPE: This 2-bit field indicates the FEC type used for PLS2 that is carried in every frame of the next frame-group. The FEC type is signaled according to the table 10.

PLS2_NEXT_MOD: This 3-bit field indicates the modulation type used for PLS2 that is carried in every frame of the next frame-group. The modulation type is signaled according to the table 11.

PLS2_NEXT_REP_FLAG: This 1-bit flag indicates whether the PLS2 repetition mode is used in the next frame-group. When this field is set to value ‘1’, the PLS2 repetition mode is activated. When this field is set to value ‘0’, the PLS2 repetition mode is deactivated.

PLS2_NEXT_REP_SIZE_CELL: This 15-bit field indicates C_(total) _(_) _(full) _(_) _(block), The size (specified as the number of QAM cells) of the collection of full coded blocks for PLS2 that is carried in every frame of the next frame-group, when PLS2 repetition is used. If repetition is not used in the next frame-group, the value of this field is equal to 0. This value is constant during the entire duration of the current frame-group.

PLS2_NEXT_REP_STAT_SIZE_BIT: This 14-bit field indicates the size, in bits, of the PLS2-STAT for the next frame-group. This value is constant in the current frame-group.

PLS2_NEXT_REP_DYN_SIZE_BIT: This 14-bit field indicates the size, in bits, of the PLS2-DYN for the next frame-group. This value is constant in the current frame-group.

PLS2_AP_MODE: This 2-bit field indicates whether additional parity is provided for PLS2 in the current frame-group. This value is constant during the entire duration of the current frame-group. The below table 12 gives the values of this field. When this field is set to ‘00’, additional parity is not used for the PLS2 in the current frame-group.

TABLE 12 Value PLS2-AP mode 00 AP is not provided 01 AP1 mode 10~11 Reserved

PLS2_AP_SIZE_CELL: This 15-bit field indicates the size (specified as the number of QAM cells) of the additional parity bits of the PLS2. This value is constant during the entire duration of the current frame-group.

PLS2_NEXT_AP_MODE: This 2-bit field indicates whether additional parity is provided for PLS2 signaling in every frame of next frame-group. This value is constant during the entire duration of the current frame-group. The table 12 defines the values of this field

PLS2_NEXT_AP_SIZE_CELL: This 15-bit field indicates the size (specified as the number of QAM cells) of the additional parity bits of the PLS2 in every frame of the next frame-group. This value is constant during the entire duration of the current frame-group.

RESERVED: This 32-bit field is reserved for future use.

CRC_32: A 32-bit error detection code, which is applied to the entire PLS1 signaling.

FIG. 14 illustrates PLS2 data according to an embodiment of the present invention.

FIG. 14 illustrates PLS2-STAT data of the PLS2 data. The PLS2-STAT data are the same within a frame-group, while the PLS2-DYN data provide information that is specific for the current frame.

The details of fields of the PLS2-STAT data are as follows:

FIC_FLAG: This 1-bit field indicates whether the FIC is used in the current frame-group. If this field is set to ‘1’, the FIC is provided in the current frame. If this field set to ‘0’, the FIC is not carried in the current frame. This value is constant during the entire duration of the current frame-group.

AUX_FLAG: This 1-bit field indicates whether the auxiliary stream(s) is used in the current frame-group. If this field is set to ‘1’, the auxiliary stream is provided in the current frame. If this field set to ‘0’, the auxiliary stream is not carried in the current frame. This value is constant during the entire duration of current frame-group.

NUM_DP: This 6-bit field indicates the number of DPs carried within the current frame. The value of this field ranges from 1 to 64, and the number of DPs is NUM_DP+1.

DP_ID: This 6-bit field identifies uniquely a DP within a PHY profile.

DP_TYPE: This 3-bit field indicates the type of the DP. This is signaled according to the below table 13.

TABLE 13 Value DP Type 000 DP Type 1 001 DP Type 2 010~111 reserved

DP_GROUP_ID: This 8-bit field identifies the DP group with which the current DP is associated. This can be used by a receiver to access the DPs of the service components associated with a particular service, which will have the same DP_GROUP_ID.

BASE_DP_ID: This 6-bit field indicates the DP carrying service signaling data (such as PSI/SI) used in the Management layer. The DP indicated by BASE_DP_ID may be either a normal DP carrying the service signaling data along with the service data or a dedicated DP carrying only the service signaling data

DP_FEC_TYPE: This 2-bit field indicates the FEC type used by the associated DP. The FEC type is signaled according to the below table 14.

TABLE 14 Value FEC_TYPE 00 16K LDPC 01 64K LDPC 10~11 Reserved

DP_COD: This 4-bit field indicates the code rate used by the associated DP. The code rate is signaled according to the below table 15.

TABLE 15 Value Code rate 0000 5/15 0001 6/15 0010 7/15 0011 8/15 0100 9/15 0101 10/15  0110 11/15  0111 12/15  1000 13/15  1001~1111 Reserved

DP_MOD: This 4-bit field indicates the modulation used by the associated DP. The modulation is signaled according to the below table 16.

TABLE 16 Value Modulation 0000 QPSK 0001 QAM-16 0010 NUQ-64 0011 NUQ-256 0100 NUQ-1024 0101 NUC-16 0110 NUC-64 0111 NUC-256 1000 NUC-1024 1001~1111 reserved

DP_SSD_FLAG: This 1-bit field indicates whether the SSD mode is used in the associated DP. If this field is set to value ‘1’, SSD is used. If this field is set to value ‘0’, SSD is not used.

The following field appears only if PHY_PROFILE is equal to ‘010’, which indicates the advanced profile:

DP_MIMO: This 3-bit field indicates which type of MIMO encoding process is applied to the associated DP. The type of MIMO encoding process is signaled according to the table 17.

TABLE 17 Value MIMO encoding 000 FR-SM 001 FRFD-SM 010~111 reserved

DP_TI_TYPE: This 1-bit field indicates the type of time-interleaving. A value of ‘0’ indicates that one TI group corresponds to one frame and contains one or more TI-blocks. A value of ‘1’ indicates that one TI group is carried in more than one frame and contains only one TI-block.

DP_TI_LENGTH: The use of this 2-bit field (the allowed values are only 1, 2, 4, 8) is determined by the values set within the DP_TI_TYPE field as follows:

If the DP_TI_TYPE is set to the value ‘1’, this field indicates P_(I), the number of the frames to which each TI group is mapped, and there is one TI-block per TI group (N_(TI)=1). The allowed P_(I) values with 2-bit field are defined in the below table 18.

If the DP_TI_TYPE is set to the value ‘0’, this field indicates the number of TI-blocks N_(H) per TI group, and there is one TI group per frame (P_(I)=1). The allowed P_(I) values with 2-bit field are defined in the below table 18.

TABLE 18 2-bit field P_(I) N_(TI) 00 1 1 01 2 2 10 4 3 11 8 4

DP_FRAME_INTERVAL: This 2-bit field indicates the frame interval (I_(JUMP)) within the frame-group for the associated DP and the allowed values are 1, 2, 4, 8 (the corresponding 2-bit field is ‘00’, ‘01’, ‘10’, or ‘11’, respectively). For DPs that do not appear every frame of the frame-group, the value of this field is equal to the interval between successive frames. For example, if a DP appears on the frames 1, 5, 9, 13, etc., this field is set to ‘4’. For DPs that appear in every frame, this field is set to ‘1’.

DP_TI_BYPASS: This 1-bit field determines the availability of time interleaver. If time interleaving is not used for a DP, it is set to ‘1’. Whereas if time interleaving is used it is set to ‘0’.

DP_FIRST_FRAME_IDX: This 5-bit field indicates the index of the first frame of the super-frame in which the current DP occurs. The value of DP_FIRST_FRAME_IDX ranges from 0 to 31

DP_NUM_BLOCK_MAX: This 10-bit field indicates the maximum value of DP_NUM_BLOCKS for this DP. The value of this field has the same range as DP_NUM_BLOCKS.

DP_PAYLOAD_TYPE: This 2-bit field indicates the type of the payload data carried by the given DP. DP_PAYLOAD_TYPE is signaled according to the below table 19.

TABLE 19 Value Payload Type 00 TS. 01 IP 10 GS 11 reserved

DP_INTBAND_MODE: This 2-bit field indicates whether the current DP carries in-band signaling information. The in-band signaling type is signaled according to the below table 20.

TABLE 20 Value In-band mode 00 In-band signaling is not carried. 01 INBAND-PLS is carried only 10 INBAND-ISSY is carried only 11 INBAND-PLS and INBAND-ISSY are carried

DP_PROTOCOL_TYPE: This 2-bit field indicates the protocol type of the payload carried by the given DP. It is signaled according to the below table 21 when input payload types are selected.

TABLE 21 If DP_PAYLOAD_TYPE If DP_PAYLOAD_TYPE If DP_PAYLOAD_TYPE Value Is TS Is IP Is GS 00 MPEG2-TS IPv4 (Note) 01 Reserved IPv6 Reserved 10 Reserved Reserved Reserved 11 Reserved Reserved Reserved

DP_CRC_MODE: This 2-bit field indicates whether CRC encoding is used in the Input Formatting block. The CRC mode is signaled according to the below table 22.

TABLE 22 Value CRC mode 00 Not used 01 CRC-8 10 CRC-16 11 CRC-32

DNP_MODE: This 2-bit field indicates the null-packet deletion mode used by the associated DP when DP_PAYLOAD_TYPE is set to TS (‘00’). DNP_MODE is signaled according to the below table 23. If DP_PAYLOAD_TYPE is not TS (‘00’), DNP_MODE is set to the value ‘00’.

TABLE 23 Value Null-packet deletion mode 00 Not used 01 DNP-NORMAL 10 DNP-OFFSET 11 reserved

ISSY_MODE: This 2-bit field indicates the ISSY mode used by the associated DP when DP_PAYLOAD_TYPE is set to TS (‘00’). The ISSY_MODE is signaled according to the below table 24 If DP_PAYLOAD_TYPE is not TS (‘00’), ISSY_MODE is set to the value ‘00’.

TABLE 24 Value ISSY mode 00 Not used 01 ISSY-UP 10 ISSY-BBF 11 reserved

HC_MODE_TS: This 2-bit field indicates the TS header compression mode used by the associated DP when DP_PAYLOAD_TYPE is set to TS (‘00’). The HC_MODE_TS is signaled according to the below table 25.

TABLE 25 Value Header compression mode 00 HC_MODE_TS 1 01 HC_MODE_TS 2 10 HC_MODE_TS 3 11 HC_MODE_TS 4

HC_MODE_IP: This 2-bit field indicates the IP header compression mode when DP_PAYLOAD_TYPE is set to IP (‘01’). The HC_MODE_IP is signaled according to the below table 26.

TABLE 26 Value Header compression mode 00 No compression 01 HC_MODE_IP 1 10~11 reserved

PID: This 13-bit field indicates the PID number for TS header compression when DP_PAYLOAD_TYPE is set to TS (‘00’) and HC_MODE_TS is set to ‘01’ or ‘10’.

RESERVED: This 8-bit field is reserved for future use.

The following field appears only if FIC_FLAG is equal to ‘I’:

FIC_VERSION: This 8-bit field indicates the version number of the FIC.

FIC_LENGTH_BYTE: This 13-bit field indicates the length, in bytes, of the FIC.

RESERVED: This 8-bit field is reserved for future use.

The following field appears only if AUX_FLAG is equal to ‘I’:

NUM_AUX: This 4-bit field indicates the number of auxiliary streams. Zero means no auxiliary streams are used.

AUX_CONFIG_RFU: This 8-bit field is reserved for future use.

AUX_STREAM_TYPE: This 4-bit is reserved for future use for indicating the type of the current auxiliary stream.

AUX_PRIVATE_CONFIG: This 28-bit field is reserved for future use for signaling auxiliary streams.

FIG. 15 illustrates PLS2 data according to another embodiment of the present invention.

FIG. 15 illustrates PLS2-DYN data of the PLS2 data. The values of the PLS2-DYN data may change during the duration of one frame-group, while the size of fields remains constant.

The details of fields of the PLS2-DYN data are as follows:

FRAME_INDEX: This 5-bit field indicates the frame index of the current frame within the super-frame. The index of the first frame of the super-frame is set to ‘0’.

PLS_CHANGE_COUNTER: This 4-bit field indicates the number of super-frames ahead where the configuration will change. The next super-frame with changes in the configuration is indicated by the value signaled within this field. If this field is set to the value ‘0000’, it means that no scheduled change is foreseen: e.g., value ‘1’ indicates that there is a change in the next super-frame.

FIC_CHANGE_COUNTER: This 4-bit field indicates the number of super-frames ahead where the configuration (i.e., the contents of the FIC) will change. The next super-frame with changes in the configuration is indicated by the value signaled within this field. If this field is set to the value ‘0000’, it means that no scheduled change is foreseen: e.g. value ‘0001’ indicates that there is a change in the next super-frame.

RESERVED: This 16-bit field is reserved for future use.

The following fields appear in the loop over NUM_DP, which describe the parameters associated with the DP carried in the current frame.

DP_ID: This 6-bit field indicates uniquely the DP within a PHY profile.

DP_START: This 15-bit (or 13-bit) field indicates the start position of the first of the DPs using the DPU addressing scheme. The DP_START field has differing length according to the PHY profile and FFT size as shown in the below table 27.

TABLE 27 DP_START field size PHY profile 64K 16K Base 13 bit 15 bit Handheld — 13 bit Advanced 13 bit 15 bit

DP_NUM_BLOCK: This 10-bit field indicates the number of FEC blocks in the current TI group for the current DP. The value of DP_NUM_BLOCK ranges from 0 to 1023

RESERVED: This 8-bit field is reserved for future use.

The following fields indicate the FIC parameters associated with the EAC.

EAC_FLAG: This 1-bit field indicates the existence of the EAC in the current frame. This bit is the same value as the EAC_FLAG in the preamble.

EAS_WAKE_UP_VERSION_NUM: This 8-bit field indicates the version number of a wake-up indication.

If the EAC_FLAG field is equal to ‘1’, the following 12 bits are allocated for EAC_LENGTH_BYTE field. If the EAC_FLAG field is equal to ‘0’, the following 12 bits are allocated for EAC_COUNTER.

EAC_LENGTH_BYTE: This 12-bit field indicates the length, in byte, of the EAC.

EAC_COUNTER: This 12-bit field indicates the number of the frames before the frame where the EAC arrives.

The following field appears only if the AUX_FLAG field is equal to ‘1’:

AUX_PRIVATE_DYN: This 48-bit field is reserved for future use for signaling auxiliary streams. The meaning of this field depends on the value of AUX_STREAM_TYPE in the configurable PLS2-STAT.

CRC_32: A 32-bit error detection code, which is applied to the entire PLS2.

FIG. 16 illustrates a logical structure of a frame according to an embodiment of the present invention.

As above mentioned, the PLS, EAC, FIC, DPs, auxiliary streams and dummy cells are mapped into the active carriers of the OFDM symbols in the frame. The PLS1 and PLS2 are first mapped into one or more FSS(s). After that, EAC cells, if any, are mapped immediately following the PLS field, followed next by FIC cells, if any. The DPs are mapped next after the PLS or EAC, FIC, if any. Type 1 DPs follows first, and Type 2 DPs next. The details of a type of the DP will be described later. In some case, DPs may carry some special data for EAS or service signaling data. The auxiliary stream or streams, if any, follow the DPs, which in turn are followed by dummy cells. Mapping them all together in the above mentioned order, i.e. PLS, EAC, FIC, DPs, auxiliary streams and dummy data cells exactly fill the cell capacity in the frame.

FIG. 17 illustrates PLS mapping according to an embodiment of the present invention.

PLS cells are mapped to the active carriers of FSS(s). Depending on the number of cells occupied by PLS, one or more symbols are designated as FSS(s), and the number of FSS(s) N_(FSS) is signaled by NUM_FSS in PLS1. The FSS is a special symbol for carrying PLS cells. Since robustness and latency are critical issues in the PLS, the FSS(s) has higher density of pilots allowing fast synchronization and frequency-only interpolation within the FSS.

PLS cells are mapped to active carriers of the N_(FSS) FSS(s) in a top-down manner as shown in an example in FIG. 17. The PLS1 cells are mapped first from the first cell of the first FSS in an increasing order of the cell index. The PLS2 cells follow immediately after the last cell of the PLS1 and mapping continues downward until the last cell index of the first FSS. If the total number of required PLS cells exceeds the number of active carriers of one FSS, mapping proceeds to the next FSS and continues in exactly the same manner as the first FSS.

After PLS mapping is completed, DPs are carried next. If EAC, FIC or both are present in the current frame, they are placed between PLS and “normal” DPs.

FIG. 18 illustrates EAC mapping according to an embodiment of the present invention.

EAC is a dedicated channel for carrying EAS messages and links to the DPs for EAS. EAS support is provided but EAC itself may or may not be present in every frame. EAC, if any, is mapped immediately after the PLS2 cells. EAC is not preceded by any of the FIC, DPs, auxiliary streams or dummy cells other than the PLS cells. The procedure of mapping the EAC cells is exactly the same as that of the PLS.

The EAC cells are mapped from the next cell of the PLS2 in increasing order of the cell index as shown in the example in FIG. 18. Depending on the EAS message size, EAC cells may occupy a few symbols, as shown in FIG. 18.

EAC cells follow immediately after the last cell of the PLS2, and mapping continues downward until the last cell index of the last FSS. If the total number of required EAC cells exceeds the number of remaining active carriers of the last FSS mapping proceeds to the next symbol and continues in exactly the same manner as FSS(s). The next symbol for mapping in this case is the normal data symbol, which has more active carriers than a FSS.

After EAC mapping is completed, the FIC is carried next, if any exists. If FIC is not transmitted (as signaled in the PLS2 field), DPs follow immediately after the last cell of the EAC.

FIG. 19 illustrates FIC mapping according to an embodiment of the present invention.

(a) shows an example mapping of FIC cell without EAC and (b) shows an example mapping of FIC cell with EAC.

FIC is a dedicated channel for carrying cross-layer information to enable fast service acquisition and channel scanning. This information primarily includes channel binding information between DPs and the services of each broadcaster. For fast scan, a receiver can decode FIC and obtain information such as broadcaster ID, number of services, and BASE_DP_ID. For fast service acquisition, in addition to FIC, base DP can be decoded using BASE_DP_ID. Other than the content it carries, a base DP is encoded and mapped to a frame in exactly the same way as a normal DP. Therefore, no additional description is required for a base DP. The FIC data is generated and consumed in the Management Layer. The content of FIC data is as described in the Management Layer specification.

The FIC data is optional and the use of FIC is signaled by the FIC_FLAG parameter in the static part of the PLS2. If FIC is used, FIC_FLAG is set to ‘1’ and the signaling field for FIC is defined in the static part of PLS2. Signaled in this field are FIC_VERSION, and FIC_LENGTH_BYTE. FIC uses the same modulation, coding and time interleaving parameters as PLS2. FIC shares the same signaling parameters such as PLS2_MOD and PLS2_FEC. FIC data, if any, is mapped immediately after PLS2 or EAC if any. FIC is not preceded by any normal DPs, auxiliary streams or dummy cells. The method of mapping FIC cells is exactly the same as that of EAC which is again the same as PLS.

Without EAC after PLS, FIC cells are mapped from the next cell of the PLS2 in an increasing order of the cell index as shown in an example in (a). Depending on the FIC data size, FIC cells may be mapped over a few symbols, as shown in (b).

FIC cells follow immediately after the last cell of the PLS2, and mapping continues downward until the last cell index of the last FSS. If the total number of required FIC cells exceeds the number of remaining active carriers of the last FSS, mapping proceeds to the next symbol and continues in exactly the same manner as FSS(s). The next symbol for mapping in this case is the normal data symbol which has more active carriers than a FSS.

If EAS messages are transmitted in the current frame, EAC precedes FIC, and FIC cells are mapped from the next cell of the EAC in an increasing order of the cell index as shown in (b).

After FIC mapping is completed, one or more DPs are mapped, followed by auxiliary streams, if any, and dummy cells.

FIG. 20 illustrates a type of DP according to an embodiment of the present invention.

(a) shows type 1 DP and (b) shows type 2 DP.

After the preceding channels, i.e., PLS, EAC and FIC, are mapped, cells of the DPs are mapped. A DP is categorized into one of two types according to mapping method:

Type 1 DP: DP is mapped by TDM

Type 2 DP: DP is mapped by FDM

The type of DP is indicated by DP_TYPE field in the static part of PLS2. FIG. 20 illustrates the mapping orders of Type 1 DPs and Type 2 DPs. Type 1 DPs are first mapped in the increasing order of cell index, and then after reaching the last cell index, the symbol index is increased by one. Within the next symbol, the DP continues to be mapped in the increasing order of cell index starting from p=0. With a number of DPs mapped together in one frame, each of the Type 1 DPs are grouped in time, similar to TDM multiplexing of DPs.

Type 2 DPs are first mapped in the increasing order of symbol index, and then after reaching the last OFDM symbol of the frame, the cell index increases by one and the symbol index rolls back to the first available symbol and then increases from that symbol index. After mapping a number of DPs together in one frame, each of the Type 2 DPs are grouped in frequency together, similar to FDM multiplexing of DPs.

Type 1 DPs and Type 2 DPs can coexist in a frame if needed with one restriction; Type 1 DPs always precede Type 2 DPs. The total number of OFDM cells carrying Type 1 and Type 2 DPs cannot exceed the total number of OFDM cells available for transmission of DPs:

D _(DP1) +D _(DP2) ≦D _(DP)  [Expression 2]

where D_(DP1) is the number of OFDM cells occupied by Type 1 DPs, D_(DP2) is the number of cells occupied by Type 2 DPs. Since PLS, EAC, FIC are all mapped in the same way as Type 1 DP, they all follow “Type 1 mapping rule”. Hence, overall, Type 1 mapping always precedes Type 2 mapping.

FIG. 21 illustrates DP mapping according to an embodiment of the present invention.

(a) shows an addressing of OFDM cells for mapping type 1 DPs and (b) shows an addressing of OFDM cells for mapping for type 2 DPs.

Addressing of OFDM cells for mapping Type 1 DPs (0, . . . , D_(DP1)−1) is defined for the active data cells of Type 1 DPs. The addressing scheme defines the order in which the cells from the TIs for each of the Type 1 DPs are allocated to the active data cells. It is also used to signal the locations of the DPs in the dynamic part of the PLS2.

Without EAC and FIC, address 0 refers to the cell immediately following the last cell carrying PLS in the last FSS. If EAC is transmitted and FIC is not in the corresponding frame, address 0 refers to the cell immediately following the last cell carrying EAC. If FIC is transmitted in the corresponding frame, address 0 refers to the cell immediately following the last cell carrying FIC. Address 0 for Type 1 DPs can be calculated considering two different cases as shown in (a). In the example in (a), PLS, EAC and FIC are assumed to be all transmitted. Extension to the cases where either or both of EAC and FIC are omitted is straightforward. If there are remaining cells in the FSS after mapping all the cells up to FIC as shown on the left side of (a).

Addressing of OFDM cells for mapping Type 2 DPs (0, D_(DP2)−1) is defined for the active data cells of Type 2 DPs. The addressing scheme defines the order in which the cells from the TIs for each of the Type 2 DPs are allocated to the active data cells. It is also used to signal the locations of the DPs in the dynamic part of the PLS2.

Three slightly different cases are possible as shown in (b). For the first case shown on the left side of (b), cells in the last FSS are available for Type 2 DP mapping. For the second case shown in the middle, FIC occupies cells of a normal symbol, but the number of FIC cells on that symbol is not larger than C_(FSS). The third case, shown on the right side in (b), is the same as the second case except that the number of FIC cells mapped on that symbol exceeds C_(FSS)

The extension to the case where Type 1 DP(s) precede Type 2 DP(s) is straightforward since PLS, EAC and FIC follow the same “Type 1 mapping rule” as the Type 1 DP(s).

A data pipe unit (DPU) is a basic unit for allocating data cells to a DP in a frame.

A DPU is defined as a signaling unit for locating DPs in a frame. A Cell Mapper 7010 may map the cells produced by the TIs for each of the DPs. A Time interleaver 5050 outputs a series of TI-blocks and each TI-block comprises a variable number of XFECBLOCKs which is in turn composed of a set of cells. The number of cells in an XFECBLOCK, N_(cells), is dependent on the FECBLOCK size, N_(ldpc), and the number of transmitted bits per constellation symbol. A DPU is defined as the greatest common divisor of all possible values of the number of cells in a XFECBLOCK, N_(cells), supported in a given PHY profile. The length of a DPU in cells is defined as L_(DPU). Since each PHY profile supports different combinations of FECBLOCK size and a different number of bits per constellation symbol, L_(DPU) is defined on a PHY profile basis.

FIG. 22 illustrates an FEC structure according to an embodiment of the present invention.

FIG. 22 illustrates an FEC structure according to an embodiment of the present invention before bit interleaving. As above mentioned, Data FEC encoder may perform the FEC encoding on the input BBF to generate FECBLOCK procedure using outer coding (BCH), and inner coding (LDPC). The illustrated FEC structure corresponds to the FECBLOCK. Also, the FECBLOCK and the FEC structure have same value corresponding to a length of LDPC codeword.

The BCH encoding is applied to each BBF (K_(bch) bits), and then LDPC encoding is applied to BCH-encoded BBF (K_(ldpc) bits=N_(bch) bits) as illustrated in FIG. 22.

The value of N_(ldpc) is either 64800 bits (long FECBLOCK) or 16200 bits (short FECBLOCK).

The below table 28 and table 29 show FEC encoding parameters for a long FECBLOCK and a short FECBLOCK, respectively.

TABLE 28 BCH error LDPC correction Rate N_(ldpc) K_(ldpc) K_(bch) capability N_(bch) − K_(bch) 5/15 64800 21600 21408 12 192 6/15 25920 25728 7/15 30240 30048 8/15 34560 34368 9/15 38880 38688 10/15  43200 43008 11/15  47520 47328 12/15  51840 51648 13/15  56160 55968

TABLE 29 BCH error LDPC correction Rate N_(ldpc) K_(ldpc) K_(bch) capability N_(bch) − K_(bch) 5/15 16200 5400 5232 12 168 6/15 6480 6312 7/15 7560 7392 8/15 8640 8472 9/15 9720 9552 10/15  10800 10632 11/15  11880 11712 12/15  12960 12792 13/15  14040 13872

The details of operations of the BCH encoding and LDPC encoding are as follows:

A 12-error correcting BCH code is used for outer encoding of the BBF. The BCH generator polynomial for short FECBLOCK and long FECBLOCK are obtained by multiplying together all polynomials.

LDPC code is used to encode the output of the outer BCH encoding. To generate a completed B_(ldpc) (FECBLOCK), P_(ldpc) (parity bits) is encoded systematically from each I_(ldpc) (BCH-encoded BBF), and appended to I_(ldpc). The completed B_(ldpc) (FECBLOCK) are expressed as follow Expression.

B _(ldpc) =[I _(ldpc) P _(ldpc) ]=[i ₀ ,i ₁ , . . . ,i _(K) _(ldpc) ⁻¹ ,p ₀ ,p ₁ , . . . ,p _(N) _(ldpc) _(−K) _(ldpc) ⁻¹]  [Expression 3]

The parameters for long FECBLOCK and short FECBLOCK are given in the above table 28 and 29, respectively.

The detailed procedure to calculate N_(ldpc)−K_(ldpc) parity bits for long FECBLOCK, is as follows:

1) Initialize the parity bits,

p ₀ =p ₁ =q ₂ = . . . =p _(N) _(ldpc) _(−K) _(ldpc) ⁻¹=0  [Expression 4]

2) Accumulate the first information bit−i₀, at parity bit addresses specified in the first row of an addresses of parity check matrix. The details of addresses of parity check matrix will be described later. For example, for rate 13/15:

p ₉₈₃ =p ₉₈₃ ⊕i ₀ p ₂₈₁₅ =p ₂₈₁₅ ⊕i ₀

p ₄₈₃₇ =p ₄₈₃₇ ⊕i ₀ p ₄₉₈₉ =p ₄₉₈₉ ⊕i ₀

p ₆₁₃₈ =p ₆₁₃₈ ⊕i ₀ p ₆₄₅₈ =p ₆₄₅₈ ⊕i ₀

p ₆₉₂₁ =p ₆₉₂₁ ⊕i ₀ p ₆₉₇₄ =p ₆₉₇₄ ⊕i ₀

p ₇₅₇₂ =p ₇₅₇₂ ⊕i ₀ p ₈₂₆₀ =p ₈₂₆₀ ⊕i ₀

p ₈₄₉₆ =p ₈₄₉₆ ⊕i ₀  [Expression 5]

3) For the next 359 information bits, i_(s), s=1, 2, . . . , 359 accumulate i_(s) at parity bit addresses using following Expression.

{x+(s mod 360)×Q _(ldpc)} mod(N _(ldpc) −K _(ldpc))  [Expression 6]

where x denotes the address of the parity bit accumulator corresponding to the first bit i₀, and Q_(ldpc) is a code rate dependent constant specified in the addresses of parity check matrix. Continuing with the example, Q_(ldpc)=24 for rate 13/15, so for information bit i₁, the following operations are performed:

p ₁₀₀₇ =p ₁₀₀₇ ⊕i ₁ p ₂₈₃₉ =p ₂₈₃₉ ⊕i ₁

p ₄₈₆₁ =p ₄₈₆₁ ⊕i ₁ p ₅₀₁₃ =p ₅₀₁₃ ⊕i ₁

p ₆₁₆₂ =p ₆₁₆₂ ⊕i ₁ p ₆₄₈₂ =p ₆₄₈₂ ⊕i ₁

p ₆₉₄₅ =p ₆₉₄₅ ⊕i ₁ p ₆₉₉₈ =p ₆₉₉₈ ⊕i ₁

p ₇₅₉₆ =p ₇₅₉₆ ⊕i ₁ p ₈₂₈₄ =p ₈₂₈₄ ⊕i ₁

p ₈₅₂₀ =p ₈₅₂₀ ⊕i ₁  [Expression 7]

4) For the 361^(st) information bit i₃₆₀, the addresses of the parity bit accumulators are given in the second row of the addresses of parity check matrix. In a similar manner the addresses of the parity bit accumulators for the following 359 information bits i_(s), s=361, 362, . . . , 719 are obtained using the Expression 6, where x denotes the address of the parity bit accumulator corresponding to the information bit i₃₆₀, i.e., the entries in the second row of the addresses of parity check matrix.

5) In a similar manner, for every group of 360 new information bits, a new row from addresses of parity check matrixes used to find the addresses of the parity bit accumulators.

After all of the information bits are exhausted, the final parity bits are obtained as follows:

6) Sequentially perform the following operations starting with i=1

p _(i) =p _(i) ⊕p _(i-1) ,i=1,2, . . . ,N _(ldpc) −K _(ldpc)−1  [Expression 8]

where final content of p_(i), i=0, 1, . . . N_(ldpc)−K_(ldpc)−1 is equal to the parity bit p_(i).

TABLE 30 Code Rate Q_(ldpc) 5/15 120 6/15 108 7/15 96 8/15 84 9/15 72 10/15  60 11/15  48 12/15  36 13/15  24

This LDPC encoding procedure for a short FECBLOCK is in accordance with t LDPC encoding procedure for the long FECBLOCK, except replacing the table 30 with table 31, and replacing the addresses of parity check matrix for the long FECBLOCK with the addresses of parity check matrix for the short FECBLOCK.

TABLE 31 Code Rate Q_(ldpc) 5/15 30 6/15 27 7/15 24 8/15 21 9/15 18 10/15  15 11/15  12 12/15  9 13/15  6

FIG. 23 illustrates a bit interleaving according to an embodiment of the present invention.

The outputs of the LDPC encoder are bit-interleaved, which consists of parity interleaving followed by Quasi-Cyclic Block (QCB) interleaving and inner-group interleaving.

(a) shows Quasi-Cyclic Block (QCB) interleaving and (b) shows inner-group interleaving.

The FECBLOCK may be parity interleaved. At the output of the parity interleaving, the LDPC codeword consists of 180 adjacent QC blocks in a long FECBLOCK and 45 adjacent QC blocks in a short FECBLOCK. Each QC block in either a long or short FECBLOCK consists of 360 bits. The parity interleaved LDPC codeword is interleaved by QCB interleaving. The unit of QCB interleaving is a QC block. The QC blocks at the output of parity interleaving are permutated by QCB interleaving as illustrated in FIG. 23, where N_(cells)=64800/η_(mod) or 16200/η_(mod) according to the FECBLOCK length. The QCB interleaving pattern is unique to each combination of modulation type and LDPC code rate.

After QCB interleaving, inner-group interleaving is performed according to modulation type and order (η_(mod)) which is defined in the below table 32. The number of QC blocks for one inner-group, N_(QCB) _(_) _(IG), is also defined.

TABLE 32 Modulation type η_(mod) N_(QCB) _(—) _(IG) QAM-16 4 2 NUC-16 4 4 NUQ-64 6 3 NUC-64 6 6 NUQ-256 8 4 NUC-256 8 8 NUQ-1024 10 5 NUC-1024 10 10

The inner-group interleaving process is performed with N_(QCB) _(_) _(IG) QC blocks of the QCB interleaving output. Inner-group interleaving has a process of writing and reading the bits of the inner-group using 360 columns and N_(QCB) _(_) _(IG) rows. In the write operation, the bits from the QCB interleaving output are written row-wise. The read operation is performed column-wise to read out m bits from each row, where m is equal to 1 for NUC and 2 for NUQ.

FIG. 24 illustrates a cell-word demultiplexing according to an embodiment of the present invention.

(a) shows a cell-word demultiplexing for 8 and 12 bpcu MIMO and (b) shows a cell-word demultiplexing for 10 bpcu MIMO.

Each cell word (c_(0,1), c_(1,1), . . . , c_(ηmod-1,1)) of the bit interleaving output is demultiplexed into (d_(1,0,m), d_(1,1,m) . . . , d_(1,ηmod-1,m)) and (d_(2,0,m), d_(2,1,m) . . . , d_(2,ηmod-1,m)) as shown in (a), which describes the cell-word demultiplexing process for one XFECBLOCK.

For the 10 bpcu MIMO case using different types of NUQ for MIMO encoding, the Bit Interleaver for NUQ-1024 is re-used. Each cell word (c_(0,1), c_(1,l), . . . , c_(9,l)) of the Bit Interleaver output is demultiplexed into (d_(1,0,m), d_(1,1,m), . . . , d_(1,3,m)) and (d_(2,0,m), d_(2,1,m), . . . , d_(2,5,m)), as shown in (b).

FIG. 25 illustrates a time interleaving according to an embodiment of the present invention.

(a) to (c) show examples of TI mode.

The time interleaver operates at the DP level. The parameters of time interleaving (TI) may be set differently for each DP.

The following parameters, which appear in part of the PLS2-STAT data, configure the TI:

DP_TI_TYPE (allowed values: 0 or 1): Represents the TI mode; ‘0’ indicates the mode with multiple TI blocks (more than one TI block) per TI group. In this case, one TI group is directly mapped to one frame (no inter-frame interleaving). ‘1’ indicates the mode with only one TI block per TI group. In this case, the TI block may be spread over more than one frame (inter-frame interleaving).

DP_TI_LENGTH: If DP_TI_TYPE=‘0’, this parameter is the number of TI blocks N_(TI) per TI group. For DP_TI_TYPE=‘1’, this parameter is the number of frames P_(I) spread from one TI group.

DP_NUM_BLOCK_MAX (allowed values: 0 to 1023): Represents the maximum number of XFECBLOCKs per TI group.

DP_FRAME_INTERVAL (allowed values: 1, 2, 4, 8): Represents the number of the frames L_(JUMP) between two successive frames carrying the same DP of a given PHY profile.

DP_TI_BYPASS (allowed values: 0 or 1): If time interleaving is not used for a DP, this parameter is set to ‘1’. It is set to ‘0’ if time interleaving is used.

Additionally, the parameter DP_NUM_BLOCK from the PLS2-DYN data is used to represent the number of XFECBLOCKs carried by one TI group of the DP.

When time interleaving is not used for a DP, the following TI group, time interleaving operation, and TI mode are not considered. However, the Delay Compensation block for the dynamic configuration information from the scheduler will still be required. In each DP, the XFECBLOCKs received from the SSD/MIMO encoding are grouped into TI groups. That is, each TI group is a set of an integer number of XFECBLOCKs and will contain a dynamically variable number of XFECBLOCKs. The number of XFECBLOCKs in the TI group of index n is denoted by N_(xBLOCK) _(_) _(Group)(n) and is signaled as DP_NUM_BLOCK in the PLS2-DYN data. Note that N_(xBLOCK) _(_) _(Group)(n) may vary from the minimum value of 0 to the maximum value N_(xBLOCK) _(_) _(Group) _(_) _(MAX) (corresponding to DP_NUM_BLOCK_MAX) of which the largest value is 1023.

Each TI group is either mapped directly onto one frame or spread over P_(i) frames. Each TI group is also divided into more than one TI blocks (N_(TI)), where each TI block corresponds to one usage of time interleaver memory. The TI blocks within the TI group may contain slightly different numbers of XFECBLOCKs. If the TI group is divided into multiple TI blocks, it is directly mapped to only one frame. There are three options for time interleaving (except the extra option of skipping the time interleaving) as shown in the below table 33.

TABLE 33 Modes Descriptions Option-1 Each TI group contains one TI block and is mapped directly to one frame as shown in (a). This option is signaled in the PLS2-STAT by DP_TI_TYPE = ‘0’ and DP_TI_LENGTH = ‘1’(N_(TI) = 1). Option-2 Each TI group contains one TI block and is mapped to more than one frame. (b) shows an example, where one TI group is mapped to two frames, i.e., DP_TI_LENGTH = ‘2’ (P_(I) = 2) and DP_FRAME_INTERVAL (I_(JUMP) = 2). This provides greater time diversity for low data-rate services. This option is signaled in the PLS2-STAT by DP_TI_TYPE = ‘1’. Option-3 Each TI group is divided into multiple TI blocks and is mapped directly to one frame as shown in (c). Each TI block may use full TI memory, so as to provide the maximum bit-rate for a DP. This option is signaled in the PLS2-STAT signaling by DP_TI_TYPE = ‘0’ and DP_TI_LENGTH = N_(TI), while P_(I) = 1.

In each DP, the TI memory stores the input XFECBLOCKs (output XFECBLOCKs from the SSD/MIMO encoding block). Assume that input XFECBLOCKs are defined as

(d_(n, s, 0, 0), d_(n, s, 0, 1), …  , d_(n, s, 0, N_(cells) − 1), d_(n, s, 1, 0), …  , d_(n, s, 1, N_(cells) − 1), …  , d_(n, s, N_(xBLOCK_TI)(n, s) − 1, 0), …  , d_(n, s, N_(xBLOCK_TI)(n, s) − N_(cells) − 1)),

where d_(n,s,r,q) is the qth cell of the rth XFECBLOCK in the sth TI block of the nth TI group and represents the outputs of SSD and MIMO encodings as follows.

$\mspace{79mu} {d_{n,s,r,q} = \left\{ {\begin{matrix} {f_{n,s,r,q},} & {{theoutputof}\mspace{11mu} {SSD}\mspace{14mu} \ldots \mspace{14mu} {encoding}} \\ {g_{n,s,r,q},} & {{theoutputof}\mspace{11mu} {MIMOencoding}\text{?}} \end{matrix}\text{?}\text{indicates text missing or illegible when filed}} \right.}$

In addition, assume that output XFECBLOCKs from the time interleaver are defined as

(h_(n, s, 0), h_(n, s, 1), …  , h_(n, s, i), …  , h_(n, s, N_(xBLOCK_TI)(n, s) × N_(cells) − 1)),

where h_(n,s,i) is the ith output cell (for i=0, . . . , N_(xBLOCK) _(_) _(TI) (n,s)×N_(cells)−1) in the sth TI block of the nth TI group.

Typically, the time interleaver will also act as a buffer for DP data prior to the process of frame building. This is achieved by means of two memory banks for each DP. The first TI-block is written to the first bank. The second TI-block is written to the second bank while the first bank is being read from and so on.

The TI is a twisted row-column block interleaver. For the sth TI block of the nth TI group, the number of rows N_(r) of a TI memory is equal to the number of cells N_(cells), i.e., N_(r)=N_(cells) while the number of columns N_(c) is equal to the number N_(xBLOCK) _(_) _(TI)(n,s)

FIG. 26 illustrates the basic operation of a twisted row-column block interleaver according to an embodiment of the present invention.

shows a writing operation in the time interleaver and (b) shows a reading operation in the time interleaver The first XFECBLOCK is written column-wise into the first column of the TI memory, and the second XFECBLOCK is written into the next column, and so on as shown in (a). Then, in the interleaving array, cells are read out diagonal-wise. During diagonal-wise reading from the first row (rightwards along the row beginning with the left-most column) to the last row, N_(r) cells are read out as shown in (b). In detail, assuming z_(n,s,i)(i=0, . . . , N_(r)N_(c)) as the TI memory cell position to be read sequentially, the reading process in such an interleaving array is performed by calculating the row index R_(n,s,i), the column index C_(n,s,i), and the associated twisting parameter T_(n,s,i) as follows expression.

$\begin{matrix} {{{GENERATE}\; \left( {R_{n,s,i},C_{n,s,i}} \right)} = \left\{ {{R_{n,s,i} = {{mod}\left( {i,N_{r}} \right)}},{T_{n,s,i} = {{mod}\left( {{S_{shift} \times R_{n,s,i}},N_{c}} \right)}},{C_{n,s,i} = {{mod}\left( {{T_{n,s,i} + \left\lfloor \frac{i}{N_{r}} \right\rfloor},N_{c}} \right)}}} \right\}} & \left( {{Expression}\mspace{14mu} 9} \right) \end{matrix}$

where S_(shift) is a common shift value for the diagonal-wise reading process regardless of N_(xBLOCK) _(_) _(TI)(n,s) and it is determined by N_(xBLOCK) _(_) _(TI) _(_) _(MAX) given in the PLS2-STAT as follows expression.

$\begin{matrix} {{for}\mspace{11mu} \left\{ {\begin{matrix} \begin{matrix} {N_{{{xBLOCK}\_ {TI}}{\_ {MAX}}}^{\prime} =} \\ {{N_{{{xBLOCK}\_ {TI}}{\_ {MAX}}} + 1},} \end{matrix} & {{{{if}\mspace{14mu} N_{{{xBLOCK}\_ {TI}}{\_ {MAX}}}{mod}\; 2} = 0}\;} \\ \begin{matrix} {N_{{{xBLOCK}\_ {TI}}{\_ {MAX}}}^{\prime} =} \\ {N_{{{xBLOCK}\_ {TI}}{\_ {MAX}}},} \end{matrix} & {{{if}\mspace{14mu} N_{{{xBLOCK}\_ {TI}}{\_ {MAX}}}{mod}\; 2} = 1} \end{matrix},\mspace{79mu} {S_{shift} = \frac{N_{{{xBLOCK}\_ {TI}}{\_ {MAX}}}^{\prime} - 1}{2}}} \right.} & \left( {{Expression}\mspace{14mu} 10} \right) \end{matrix}$

As a result, the cell positions to be read are calculated by a coordinate as z_(n,s,i)=N_(r)C_(n,s,i)+R_(n,s,i).

FIG. 27 illustrates an operation of a twisted row-column block interleaver according to another embodiment of the present invention.

More specifically, FIG. 27 illustrates the interleaving array in the TI memory for each TI group, including virtual XFECBLOCKs when N_(xBLOCK) _(_) _(TI)(0,0)=3, N_(xBLOCK) _(_) _(TI)(1,0)=6, N_(xBLOCK) _(_) _(TI)(2,0)=5.

The variable number N_(xBLOCK) _(_) _(TI)(n,s)=N_(r) will be less than or equal to N′_(xBLOCK) _(_) _(TI) _(_) _(MAX). Thus, in order to achieve a single-memory deinterleaving at the receiver side, regardless of N_(xBLOCK) _(_) _(TI)(n,s), the interleaving array for use in a twisted row-column block interleaver is set to the size of N_(r)×N_(c)=N_(cells)×N′_(xBLOCK) _(_) _(TI) _(_) _(MAX) by inserting the virtual XFECBLOCKs into the TI memory and the reading process is accomplished as follow expression.

[Expression 11] p = 0; for i = 0;i < N_(cells)N′_(xBLOCK) _(—) _(TI) _(—) _(MAX);i = i + 1 {GENERATE (R_(n,s,i), C_(n,s,i)); V_(i) = N_(r)C_(n,s,j) + R_(n,s,j) if V_(i) < N_(cells)N_(xBLOCK) _(—) _(TI)(n,s) { Z_(n,s,p) = V_(i); p = p + 1; } }

The number of TI groups is set to 3. The option of time interleaver is signaled in the PLS2-STAT data by DP_TI_TYPE=‘0’, DP_FRAME_INTERVAL=‘1’, and DP_TI_LENGTH=‘1’, i.e., N_(TI)=1, I_(JUMP)=1, and P_(I)=1. The number of XFECBLOCKs, each of which has N_(cells)=30 cells, per TI group is signaled in the PLS2-DYN data by N_(xBLOCK) _(_) _(TI)(0,0)=3, N_(xBLOCK) _(_) _(TI)(1,0)=6, and N_(xBLOCK) _(_) _(TI)(2,0)=5, respectively. The maximum number of XFECBLOCK is signaled in the PLS2-STAT data by N_(xBLOCK) _(_) _(Group) _(_) _(MAX), which leads to └N_(xBLOCK) _(_) _(Group) _(_) _(MAX)/N_(TI)┘=N_(xBLOCK) _(_) _(TI) _(_) _(MAX)=6.

FIG. 28 illustrates a diagonal-wise reading pattern of a twisted row-column block interleaver according to an embodiment of the present invention.

More specifically FIG. 28 shows a diagonal-wise reading pattern from each interleaving array with parameters of N′_(xBLOCK) _(_) _(TI) _(_) _(MAX)=7 and S_(shift)=(7−1)/2=3. Note that in the reading process shown as pseudocode above, if V_(i)≧N_(cells)N_(xBLOCK) _(_) _(TI)(n,s), the value of V_(i) is skipped and the next calculated value of V_(i) is used.

FIG. 29 illustrates interlaved XFECBLOCKs from each interleaving array according to an embodiment of the present invention.

FIG. 29 illustrates the interleaved XFECBLOCKs from each interleaving array with parameters of N′_(xBLOCK) _(_) _(TI) _(_) _(MAX)=7 and S_(shift)=3.

The NGH-CI described in the above figures may be referred to as a convolutional delay line. Hereinafter, the convolutional delay line will be described. In addition, the convolutional delay line may be referred to as a convolutional interleaver in the present specification. Here, convolutional interleaver that refers to the convolutional delay line may be another convolutional interleaver distinguished from a convolutional interleaver used in an S-PLP mode to be described below. In addition, the NGH-CDI described above with reference to figures may be referred to as inverse processing of the convolutional delay line. Hereinafter, a description will be given of inverse processing of the convolutional delay line.

Hereinafter, a description will be given of a time interleaver according to another embodiment of the present invention. The time interleaver according to the present embodiment may perform cell interleaving, block interleaving, convolutional delay line according to a PLP mode. An interleaver according to an embodiment of the present invention may be referred to as a time interleaver or a hybrid interleaver, and include a cell interleaver, a block interleaver, and a convolutional delay line.

The block interleaver and the convolutional delay line may be referred to as a hybrid time interleaver. The hybrid time interleaver to be described below corresponds to another example of the above-described hybrid time interleaver, and may operate according to a PLP mode.

Names, locations, etc. of respective devices may be changed by a designer.

FIG. 30 is a diagram illustrating a configuration of an interleaver according to an embodiment of the present invention. The interleaver according to the present invention may be differently configured according to a PLP mode. In other words, an interleaver of an S-PLP mode may include a cell interleaver and a convolutional interleaver. According to a given embodiment, the interleaver of the S-PLP mode may further include another interleaver between the cell interleaver and the convolutional interleaver. In addition, an interleaver of an M-PLP mode may include a cell interleaver and a hybrid time interleaver. Here, the hybrid time interleaver may include a twisted block interleaver and a convolutional delay line. As described above, the convolutional delay line may be referred to as a convolutional interleaver. According to a given embodiment, the interleaver of the M-PLP mode may further include another interleaver between the cell interleaver and the hybrid interleaver. The other interleaver may perform interleaving in various schemes according to intent of a designer.

In addition, in the present invention, multiple PLPs may be expressed by M-PLP or PLP_NUM>1, and a single PLP may be expressed by S-PLP or PLP_NUM=1. Information about a PLP mode may be transmitted through a signaling field PLP_NUM in a signal frame.

PLP_NUM according to an embodiment of the present invention may be included in a preamble or a preamble symbol in a signal frame. The preamble or the preamble symbol according to the present embodiment may include an L1 signaling field, and the above-described field PLP_NUM may be included in the L1 signaling field. A concept of the field PLP_NUM is the same as that of the field NUM_DP described above, and a name thereof may be changed by a designer.

A cell interleaver according to an embodiment of the present invention may operate according to a PLP mode, and a cell deinterleaver of a receiver corresponding to the cell interleaver may operate without a memory. The cell interleaver according to the present embodiment may be referred to as a modified cell interleaver. The modified cell interleaver may be used when the PLP mode is either the S-PLP mode or the M-PLP mode. Specifically, the cell interleaver according to the present embodiment may be omitted according to a given PLP mode, and an operation of the cell interleaver according to the present embodiment may be changed according to a given PLP mode. The modified cell interleaver according to the present embodiment may perform a linear write operation to a buffer, and a random read operation from the buffer. The modified cell interleaver may change an interleaving pattern for every FEC block or for every FEC block pair in the M-PLP mode. In addition, the modified cell interleaver may change an interleaving pattern for every FEC block or for every FEC block pair in the S-PLP mode. In addition, according to a given embodiment, the modified cell interleaver may use one interleaving pattern in the S-PLP mode, and not change a pattern. A specific operation of the cell interleaver will be described below.

After cell interleaving, the time interleaver according to the present embodiment may perform time interleaving according to a PLP mode. Specifically, when the PLP mode corresponds to multiple PLPs, the time interleaver according to the present embodiment may perform twisted block interleaving and convolutional delay line using the hybrid time interleaver.

When the PLP mode corresponds to a single PLP, the time interleaver according to the present embodiment may perform only arbitrary convolutional interleaving after cell interleaving. The arbitrary convolutional interleaving may refer to a conventional convolutional interleaver other than the above-described convolutional delay line, which may be changed by a designer.

As illustrated in the figure, when the PLP mode corresponds to the multiple PLPs, the hybrid time interleaver may include a twisted block interleaver and a convolutional delay line. In this case, a state of the twisted block interleaver may be expressed by an ON state.

When the PLP mode corresponds to the single PLP, the hybrid time interleaver may only include an arbitrary convolutional interleaver other than the twisted block interleaver. In other words, when one time interleaver is used in the S-PLP mode and the M-PLP mode, the time interleaver may include the hybrid time interleaver. Here, the twisted block interleaver included in the hybrid time interleaver may not be used in the single PLP mode. In addition, the hybrid time interleaver may operate as an arbitrary convolutional interleaver in the single PLP mode. In this instance, the twisted block interleaver may be expressed by an OFF state in the single PLP mode.

A state of the block interleaver according to an embodiment of the present invention may be changed based on the above-described field PLP_NUM.

FIG. 31 illustrates a configuration of an interleaver according to an embodiment of the present invention when the PLP mode corresponds to M-PLP.

Specifically, FIG. 31 illustrates a memory structure of the interleaver in M-PLP. A configuration and an order of the interleaver are the same as those described with reference to FIG. 30, and thus will be omitted.

As illustrated in FIG. 31, a cell interleaver and a twisted block interleaver included in the time interleaver according to the present embodiment may operate based on double memories. Specifically, the double memories include a memory bank A and a memory bank B, and TI blocks may be successively input and written to the memory back A and read from the memory bank B.

Prior to a frame building operation, the interleaver may function as a buffer in each PLP processing to create a signal frame including multiple PLPs. Memories of a twisted block interleaver (TBI) and a convolutional delay line illustrated in FIG. 31 may perform a function of the above-described buffer. In each PLP, a first TI block may be written to a first memory of the TBI. Thereafter, a second TI block may be written to a second memory of the TBI, and the first memory of the TBI may read the first TI block at the same time. At the same time, a TI block (intra-frame interleaving TI block) read from the first memory is transmitted to the memory of the convolutional delay line. The TI block may be transmitted based on schemes such as first-in-first-out (FIFO), a shift register process, etc. An intra-frame interleaving operation may be performed by the TBI. On the other hand, an inter-frame interleaving operation may be performed by the TBI and the convolutional delay line. A total memory of a twisted block, a convolutional interleaver, and a cell interleaver do not exceed a total memory allocated to a PLP. In addition, a total memory of each TI block (group) does not exceed a maximum memory size. The maximum memory size may be changed by a designer.

Operation orders of the cell interleaver and the time interleaver in the interleaver described above do not require additional mapping information in a deinterleaving operation of a broadcast signal reception apparatus as described above, and thus possibly occurring complexity may be reduced.

FIG. 32 illustrates a configuration of a deinterleaver corresponding to the operation of the interleaver described with reference to FIGS. 30 and 31. An operation of the deinterleaver according to an embodiment of the present invention may be performed in a reverse order of the operation of the interleaver described above. The deinterleaver according to the present embodiment may be differently configured according to a given PLP mode. In other words, a deinterleaver of an S-PLP mode may include a convolutional deinterleaver and a cell deinterleaver. According to a given embodiment, the deinterleaver of the S-PLP mode may further include another interleaver between the convolutional deinterleaver and the cell deinterleaver. In addition, a deinterleaver of an M-PLP mode may include a convolutional delay line, a twisted block deinterleaver and a cell deinterleaver. According to a given embodiment, the deinterleaver of the M-PLP mode may further include another deinterleaver between the twisted block deinterleaver and the cell deinterleaver. The other deinterleaver may perform deinterleaving in various schemes according to intent of a designer.

In addition, a time deinterleaver according to an embodiment of the present invention may perform time deinterleaving according to a PLP mode indicated by a field PLP_NUM. In other words, convolutional deinterleaving and cell deinterleaving may be successively performed in the S-PLP mode. Here, another deinterleaving may be further performed between convolutional deinterleaving and cell deinterleaving. In addition, convolutional delay line, twisted block deinterleaving, and cell deinterleaving may be successively performed in the M-PLP mode. Here, another deinterleaving may be further performed between twisted block deinterleaving and cell deinterleaving. In other words, the time deinterleaver may perform twisted block deinterleaving (twisted block deinterleaver operates) or may not perform twisted block deinterleaving (twisted block deinterleaver does not operate) after performing convolutional deinterleaving and convolutional delay line.

As mentioned in FIG. 30, PLP_NUM according to an embodiment of the present invention may be included in a preamble or a preamble symbol in a signal frame. The preamble or the preamble symbol according to the present embodiment may include an L1 signaling field, and the above-described field PLP_NUM may be included in the L1 signaling field. Therefore, a broadcast signal reception apparatus according to an embodiment of the present invention may perform time deinterleaving by obtaining a value of the field PLP_NUM included in the L1 signaling field.

Hereinafter, a description will be given of a detailed operation of the cell interleaver or the modified cell interleaver according to an embodiment of the present invention.

FIG. 33 illustrates a shift value applicable to a cell interleaver according to another embodiment of the present invention and an interleaving sequent according to the shift value expressed as a mathematical expression. The cell interleaver according to the present invention may operate as described above. Unlike description above, a shift value of S-PLP applied to the cell interleaver according to the present embodiment may correspond to a fixed value or a variable. When the shift value of S-PLP applied to the cell interleaver according to the present embodiment corresponds to the variable, the value may be the same as a value of the variable interleaving sequence of M-PLP described above. A shift value of M-PLP may be set to a variable similarly to description above.

In S-PLP, a broadcast signal transmission apparatus according to an embodiment of the present invention may omit an operation of the cell interleaver, and only perform an operation of the time interleaver.

A block interleaver after the cell interleaver according to an embodiment of the present invention may correspond to a twisted block interleaver or an arbitrary block interleaver. Hereinafter, a description will be given of an operation of the twisted block interleaver according to an embodiment of the present invention with reference to FIGS. 34 and 35. The block interleaver according to the present embodiment may operate after the cell interleaver as described above.

FIG. 34 shows an equation indicating a twisted reading operation after virtual FEC blocks are inserted according to an embodiment of the present invention. The equation may be applied to the twisted reading operation described above. The equation shown in the figure indicates twisted block interleaving applied using each TI block as a unit. As shown in the equation, the shift value may be calculated based on a maximum number of virtual FEC blocks included in a TI block. Parameters used for an operation of a hybrid time interleaver according to an embodiment of the present invention are determined based on a TI block having a maximum number of virtual FEC blocks in a super-frame. A TI block having a smaller number of FEC blocks than the number of FEC blocks of the TI having the maximum number of virtual FEC blocks may be present. In this case, virtual FEC blocks corresponding to the number of FEC blocks to be supplemented may be added to the corresponding TI block. Virtual FEC blocks according to an embodiment of the present invention may be inserted in front of actual FEC blocks. Thereafter, the time interleaver according to the present embodiment may interleave TI groups using one twisted row-column block interleaving rule based on virtual FEC blocks. In addition, the hybrid time interleaver according to the present embodiment may perform the above-described skip operation when a memory index corresponding to virtual FEC blocks is generated in a read operation. Thereafter, the number of FEC blocks of a TI group input during a write operation is made equal to the number of FEC blocks of a TI group output during a read operation. As a result, according to time interleaving of the present embodiment, even when a virtual FEC block is inserted to perform efficient single-memory deinterleaving in a receiver, loss of rate of actually transmitted data may not occur through a skip operation.

FIG. 35 shows an equation indicating a twisted read operation performed after virtual FEC blocks are inserted when a shift value is fixed to 1 according to an embodiment of the present invention. When the shift value is fixed to 1, a maximum number N′_(FEC) _(_) _(TI) _(_) _(max) of virtual FEC blocks is not needed. Therefore, it can be understood that the twisted read operation according to the present embodiment is performed based on the number N_(FEC) _(_) _(TI) of actual FEC blocks when the shift value is fixed to 1. As described in the foregoing, the skip operation indicated in the figure may skip virtual FEC blocks in the twisted read operation.

FIG. 36 shows an equation indicating twisted block deinterleaving of a hybrid time deinterleaver according to an embodiment of the present invention. Specifically, FIG. 36 shows an equation indicating a twisted read operation of the twisted block deinterleaver according to the present embodiment. The equation of FIG. 36 corresponds to the equation indicating the twisted read operation of the twisted block interleaver described with reference to FIG. 34. A shift value S_(R0) used for the twisted read operation of the twisted block deinterleaver according to the present embodiment may be calculated based on an equation at the bottom of FIG. 36. The twisted block deinterleaver according to the present embodiment may perform single-memory deinterleaving.

FIG. 37 shows an equation indicating twisted block deinterleaving of a hybrid time deinterleaver according to an embodiment of the present invention. Specifically, FIG. 37 shows an equation indicating a twisted read operation of the twisted block deinterleaver according to the present embodiment when the shift value S_(T) is fixed to 1. The equation of FIG. 37 corresponds to the equation indicating the twisted read operation of the twisted block interleaver described with reference to FIG. 35. A shift value S_(R,j) used for the twisted read operation of the twisted block deinterleaver according to the present embodiment may be calculated based on an equation at the bottom of FIG. 37. Likewise, the twisted block deinterleaver according to the present embodiment may perform single-memory deinterleaving.

Hereinafter, a description will be given of a detailed operation of the hybrid time interleaver/hybrid time deinterleaver according to an embodiment of the present invention with reference to FIGS. 38 to 42. The operation of the hybrid time interleaver/hybrid time deinterleaver of FIGS. 38 to 42 corresponds to an example of an operation based on the same parameter value.

FIG. 38 illustrates an operation of the hybrid time interleaver according to an embodiment of the present invention. Specifically, FIG. 38 illustrates an operation of the hybrid time interleaver including a twisted block interleaver and a convolutional delay line.

Specifically, specific values of parameters necessary for the operation of the hybrid time interleaver are indicated at the top of FIG. 38. The specific values of parameters are the same as those described at the top of FIG. 38.

An operation of the hybrid time interleaver performed when a first TI block (or a first IF) is input is illustrated at the bottom of FIG. 38. The hybrid time interleaver at the bottom of FIG. 38 operates based on the parameter values described at the top of FIG. 38. The operation of the hybrid time interleaver illustrated at the bottom of FIG. 38 may be applied when the shift value S_(T) is variable, and similarly applied even when the shift value is fixed to 1. The first TI block input to the twisted block interleaver is subjected to twisted block interleaving, and then output as twisted BI output cells. The twisted BI output cells output by applying the shift value S_(T) of 1 are as illustrated in the figure. Thereafter, the twisted BI output cells are input to the convolutional delay line. An operation of the convolutional delay line is as described above. Output cells of the convolutional delay line (convolutional delay line output cells) and a memory status of the convolutional delay line (convolutional delay line memory status) are illustrated at the bottom of FIG. 38. In other words, when the twisted BI output cells output from the twisted BI are input to the convolutional delay line, some cells may be output as output cells of the convolutional delay line and some other cells may be stored in a memory of the convolutional delay line and delayed as illustrated in the figure. The delayed cells may be output together with cells included in the second subsequent TI block.

FIG. 39 illustrates an operation of the hybrid time interleaver according to an embodiment of the present invention. When the second TI block is input to the twisted block interleaver subsequent to the first TI block, the TI block is subjected to interleaving and output as twisted BI output cells. Thereafter, the twisted BI output cells are input to the convolutional delay line. Output cells of the convolutional delay line (convolutional delay line output cells) and a memory status of the convolutional delay line (convolutional delay line memory status) are illustrated at the bottom of FIG. 39. In other words, when the twisted BI output cells with respect to the second TI block output from the twisted BI are input to the convolutional delay line, some cells may be output as output cells of the convolutional delay line and some other cells may be stored in a memory of the convolutional delay line and delayed as illustrated in the figure. Here, the output cells of the convolutional delay line may include some of the twisted BI output cells with respect to the second TI block and the twisted BI output cells with respect to the first TI block stored in the memory of the convolutional delay line.

FIG. 40 illustrates an operation of the hybrid time deinterleaver according to an embodiment of the present invention. Specifically, specific values of parameters necessary for the operation of the hybrid time deinterleaver are shown at the top of FIG. 40. The hybrid time deinterleaver according to the present embodiment may operate in reverse order of the operation of the hybrid time interleaver.

An operation of the hybrid time deinterleaver performed when first input cells are input to the convolutional delay line is illustrated at the bottom of FIG. 40. As illustrated in FIG. 40, the input cells of the convolutional delay line (convolutional delay line input cells) are the same as the output cells of the convolutional delay line of FIG. 38.

Specific operations of the convolutional delay line and the twisted block deinterleaver (BDI) are as illustrated in FIG. 40. In other words, when first input cells of the convolutional delay line are input to the convolutional delay line, some of input cells of the convolutional delay line may be output as output cells of the convolutional delay line, and some other input cells may be stored in a memory of the convolutional delay line and delayed. As illustrated in FIG. 40, output cells with respect to the first input cells of the convolutional delay line may not be output since the first input cells input to the convolutional delay line include black cells excluding data. When the output cells of the convolutional delay line are not output, input cells/output cells with respect to the twisted BDI may not be input/output. As a result, when the first TI block is input, an output cell of the time deinterleaver may not be output.

FIG. 41 illustrates an operation of the hybrid time deinterleaver according to an embodiment of the present invention. Specifically, specific values of parameters necessary for the operation of the hybrid time deinterleaver are indicated at the top of FIG. 41. FIG. 41 illustrates an operation of the hybrid time deinterleaver performed when second input cells are input to the convolutional delay line. As illustrated in FIG. 41, input cells of the convolutional delay line (convolutional delay line input cells) are the same as the output cells of the convolutional delay line of FIG. 39.

Specific operations of the convolutional delay line and the twisted BDI are as illustrated in FIG. 41. In other words, when the second input cells of the convolutional delay line are input to the convolutional delay line, some of input cells of the convolutional delay line may be output as output cells of the convolutional delay line, and some other input cells may be stored in a memory of the convolutional delay line and delayed. As illustrated in FIG. 41, the convolutional delay line may output some of the second input cells and the first input cells stored in the memory. In other words, the convolutional delay line may output cells included in the first TI block in the interleaving operation through the above described process. In addition, the convolutional delay line may store, in the memory, cells included in the second TI block in the interleaving operation among the second input cells. Output cells of the convolutional delay line may be input to the twisted BDI and stored in a memory of the twisted BDI. In this instance, output cells of the twisted BDI may not be output. As a result, even when the second TI block is input, an output cell of the time deinterleaver may not be output.

FIG. 42 illustrates an operation of the hybrid time deinterleaver according to an embodiment of the present invention. Specifically, specific values of parameters necessary for the operation of the hybrid time deinterleaver are shown at the top of FIG. 42. FIG. 42 illustrates an operation of the hybrid time deinterleaver performed when third input cells are input to the convolutional delay line. A specific operation of the twisted BID is as illustrated in FIG. 42. In other words, when it is presumed that the third input cells are input to the convolutional delay line, the twisted BDI may apply twisted block deinterleaving to cells stored in a memory of the twisted BDI. The twisted BDI may perform twisted block deinterleaving using a single memory, and output output cells of the twisted BDI as illustrated in FIG. 42. In other words, output cells of the time interleaver may be output. Here, it can be understood that the output cells of the twisted BDI are output similarly to the input cells input to the twisted BI in FIG. 38.

As described in the foregoing, the time interleaver according to the present invention may adaptively apply interleaving to a PLP mode, and operate as a hybrid time interleaver including a twisted block interleaver and a convolutional delay line.

An interleaver according to an embodiment of the present invention may be differently configured according to a PLP mode. As described in the foregoing, a time interleaver of an S-PLP mode may include a cell interleaver and/or a convolutional interleaver (CI). Here, the time interleaver of the S-PLP mode may only include the CI. Here, the CI may correspond to an arbitrary CI including a conventional CI. According to a given embodiment, the interleaver of the S-PLP mode may further include another interleaver between the cell interleaver and the convolutional interleaver. The other interleaver may perform interleaving in various schemes according to intent of a designer. Names, locations, etc. of respective devices may be changed by a designer. Hereinafter, a description will be given of a cell interleaver and a convolutional interleaver included in the time interleaver of the S-PLP mode. The cell interleaver included in the time interleaver of the S-PLP mode may be the same as the cell interleaver described with reference to FIG. 33, and a shift value of S-PLP may correspond to a fixed value or a variable.

FIG. 43 illustrates a configuration of the CI according to an embodiment of the present invention. An input signal of the CI may be expressed by input cells. As described in the foregoing, the time interleaver of the present invention may perform convolutional interleaving after performing cell interleaving in the S-PLP mode. In other words, an output signal or output cells of the cell interleaver may be defined as an input signal or input cells of the CI. The input cells of the CI may be subjected to FIFO processing. Here, a memory unit or an interleaving unit included in the CI may store one cell or two or more contiguous cells together. In other words, the memory unit or the interleaving unit included in the CI may store a pair of cells. In particular, the memory unit or the interleaving unit included in the CI may increase interleaving depth by storing two or more cells. Here, the two or more cells may be contiguous cells. In the figure, M denotes a memory included in the CI, and subscripts i and j may indicate an ith row and a jth column. In addition, the CI may include N_row rows and N_column columns. N_cell may denote the number of cells subjected to cell interleaving or a size of an FEC block. In the present specification, an FEC block used in the CI of the S-PLP mode may be referred to as an FEC frame.

FIG. 44 shows parameters used in a convolutional interleaver according to an embodiment of the present invention. A relation among parameters of N_cells, N_row, and N_column necessary for the configuration of the CI described above is as below. In Case-1 corresponding to a first case, N_column is defined as N_row−1 when N_row is given. In this instance, a value of N_row may be set to an integer multiple of N_cells. This parameter setting is advantageous in that a location of a first input cell in a memory of a convolutional deinterleaver (CDI) included in a broadcast signal reception apparatus can be fixed during an initial operation of the CDI. However, flexibility may be restricted when a parameter N_row is determined.

In Case-2 corresponding to a second case, N_column is defined as N_row−1 when N_row is given. In this instance, a value of N_row may be set to an arbitrary fixed value or a variable within a configured range of N_max_row. This parameter setting may not fix a location of a first input cell in the memory of the CDI during the initial operation of the CDI included in the broadcast signal reception apparatus. As a result, information about the location of the first input cell is needed. A broadcast signal transmission apparatus may inform the broadcast signal reception apparatus of the information using a signaling scheme including L1 signaling. Case-2 is effective in enhancing flexibility when determining the parameter N_row, and may cover a general case when compared to Case-1.

In Case-3 corresponding to a third case, a case in which N_column=N_row=0 indicates a case in which the CI is turned off. In other words, the time interleaver of the S-PLP mode according to the present embodiment may include the cell interleaver and the CI, and the CI may selectively operate or not operate according to signaled information according to a given embodiment. Hereinafter, a case in which the CI is not used for time interleaving may be expressed by a case in which the CI is turned OFF, and a case in which the CI is used for time interleaving may be expressed by a case in which the CI is turned ON.

According to the above-described cases, signaling information to be used for an operation the CDI corresponding to the CI may be defined as below. In other words, signaling information related to the CI/CDI may include maximum row size information, row size information, location information of a row to which a first cell is input, location information of an FEC block, and/or cell interleaving pattern information. The broadcast signal transmission apparatus may inform the broadcast signal reception apparatus of the information using a signaling scheme including L1 signaling.

The maximum row size information may be expressed by PLP_TI_NUM_ROW_MAX, and indicate maximum row size information of the CI/CDI used in a super-frame. The row size information may be expressed by PLP_TI_NUM_ROW, and indicate row size information of the CI/CDI used in a frame. The location information of the row to which the first cell is input may be expressed by PLP_TI_START_ROW, and indicate location information of the row to which the first cell is input during an operation of the CDI. In other words, PLP_TI_START_ROW may indicate a location of an interleaver selector at a start of each broadcast signal frame, and be indicated by L1D_CI_start_row. The FEC block location information may be expressed by PLP_TI_FECBLOCK_START or L1D_CI_fecframe_start, and indicate information about a location at which a first complete FEC block is started after the operation of the CDI. Here, the location information may refer to an index of a memory unit. Hereinafter, the first complete FEC block may be referred to as a first complete FEC frame. The equation shown in the figure may be used to obtain the FEC block location information. When PLP_TI_FECBLOCK_START is set to “don't care”, a value thereof may be obtained by multiplying N_row by N_column. In other cases, PLP_TI_FECBLOCK_START may be obtained as in the shown equation using memory values based on PLP_TI_NUM_ROW, PLP_TI_START_ROW, N_cells and N_row−1, and N_column−1. The cell interleaving pattern information may be expressed by PLP_TI_CELLINV_START, and indicate information related to a pattern of cell interleaving applied to the first complete FEC block after the operation of the CDI. A scheme of obtaining related information may be different.

FIG. 45 illustrates a method of generating signaling information and a convolutional interleaver according to an embodiment of the present invention. FIG. 45 may illustrate a configuration of time interleaving prior to a description of an operation of a CI. Referring to FIG. 45, it can be presumed that N_cells corresponding to a parameter related to a cell interleaver is set to 10, one TI group includes three FEC blocks, and a cell interleaving pattern used at this time is changed for every FEC block. In addition, it can be presumed that every frame includes 30 cells for a CI output signal. In the present specification, a time interleaving group may be referred to as a group of FEC frames.

FIG. 46 illustrates a method of acquiring signaling information related to interleaving by a broadcast signal transmission apparatus according to an embodiment of the present invention. The broadcast signal transmission apparatus may generate and transmit signaling information for initial synchronization of a CDI and a cell deinterleaver included in a broadcast signal reception apparatus. FIG. 46 illustrates a method of acquiring PLP_TI_CELLINV_START corresponding to cell interleaving pattern information and PLP_TI_FECBLOCK_START corresponding to FEC block location information. Hereinafter, it can be presumed that a scheduler included in the broadcast signal transmission apparatus has information about a cell interleaving pattern used for each cell-interleaved FEC block and an order of cells in the FEC block.

A number marked on each cell on the left side of FIG. 46 indicates an order of cell interleaving patterns used for a corresponding FEC block, and is ultimately intended for acquisition of information related to PLP_TI_CELLINV_START corresponding to cell interleaving pattern information. One cell interleaving pattern may be used for one FEC block. In other words, a cell interleaving pattern may be applied and changed using an FEC block as a unit. Therefore, each FEC block may have the same number. For example, a number “2” marked on a third FEC block of a first TI group may indicate that a second cell interleaving pattern is used. An order of cell interleaving patterns used in an actual system may be linked to an operation algorithm of a cell interleaver. In other words, the order may correspond to a factor “k” of symbol offset addition used in a DVB T2/NGH standard.

A number marked on each cell on the right side of FIG. 46 may indicate an order of cells in a corresponding FEC block, which is intended to acquire information related to PLP_TI_FECBLOCK_START corresponding to FEC block location information. For example, a number “9” marked on each FEC block of the first TI group may indicate a ninth cell of each FEC block.

In addition, signaling information such as PLP_TI_START_ROW, PLP_TI_NUM_ROW, etc. may be obtained through an operation of the CI.

FIG. 47 illustrates an operation of a convolutional interleaver according to an embodiment of the present invention. The operation may be applied to the first case and the second case of the relation among the parameters of N_cells, N_row, and N_column described above. Here, it can be presumed that the CI has a configuration in which N_row is 4 and N_column is 3.

A data cell-related CI operation is described at the top of FIG. 47. As illustrated in the figure, it is possible to show an example of acquiring three signaling information of PLP_TI_NUM_ROW_MAX, PLP_TI_NUM_ROW, PLP_TI_START_ROW, etc. in addition to data-cell interleaving.

An example of operating the CI by synchronizing a cell interleaving pattern used for every FEC block with a data cell in order to acquire signaling information related to PLP_TI_CELLINV_START is shown in the middle of FIG. 47. An example of a detailed operation and a method of acquiring information will be described below.

An example of operating the CI by synchronizing an order of cells in an FEC block with a data cell in order to acquire signaling information related to PLP_TI_FECBLOCK_START is shown at the bottom of FIG. 47. An example of a detailed operation and a method of acquiring information will be described below.

FIG. 48 illustrates a method of configuring a frame by a convolutional interleaver according to an embodiment of the present invention. In other words, a CI may configure a first frame using 30 cells after an initial operation. As illustrated in the figure, in the first frame, a first cell corresponds to a value of a memory when a switch of the CI is positioned at row 0, and a last cell corresponds to a value of the memory when the switch of the CI is positioned at row 1. In other words, in the first frame, the first cell corresponds to a value of a cell that corresponds to row 0 of FEC block 0 included in TI group 0 described above, and the last cell corresponds to a value of a cell that corresponds to row 5 of FEC block 2 included in TI group 0 described above. In this instance, in a configuration of the first frame, dummy cells of the memory may be regarded as data and included in the frame configuration rather than being discarded. Further, as illustrated in the figure, related signaling information necessary for a CDI may be defined by observing an initial CI memory status before interleaving. In other words, PLP_TI_NUM_ROW corresponding to row size information of the convolutional interleaver may be set to 4, and PLP_TI_START_ROW corresponding to location information of the row to which the first cell is input may be set to 0 as described above. In addition, PLP_TI_FECBLOCK_START corresponding to FEC block location information may be set to “don't care”. In this instance, “don't care” may indicate N_row*N_column. In addition, PLP_TI_CELLINV_START corresponding to cell interleaving pattern information may set to 0 corresponding to a pattern applied to a cell that corresponds to row 0 of FEC block 0 included in TI group 0.

FIG. 49 illustrates a method of configuring a frame by a convolutional interleaver according to an embodiment of the present invention. In other words, a CI may configure a second frame using 30 different cells positioned after the 30 cells included in the first frame. As described above, related signaling information necessary for a CDI of a broadcast signal reception apparatus may be defined by observing a CI memory status before interleaving. In other words, PLP_TI_NUM_ROW corresponding to row size information of the convolutional interleaver may be set to 4. A first cell of the second frame may have a value subsequent to a row value of a switch with respect to the last cell of the first frame. In other words, a row value of a CI switch with respect to the last cell of the first frame is 1 in the above example, and thus a CI switch with respect to the first cell of the second frame may be positioned on row 2. Therefore, PLP_TI_START_ROW corresponding to location information of a row to which the first cell is input may be set to 2 with respect to the second frame.

In addition, PLP_TI_FECBLOCK_START corresponding to FEC block location information may be set to 2 using the above-described equation. In other words, 2 may be obtained from (4-2-1)+(10-9) based on the above-described equation. In this instance, 9 may indicate a cell order value of a memory of M_3,2.

In addition, PLP_TI_CELLINV_START corresponding to cell interleaving pattern information is acquired by being synchronized with information of PLP_TI_FECBLOCK_START. In other words, in the figure, information related to PLP_TI_CELLINV_START obtained at the same location as that of PLP_TI_FECBLOCK_START may indicate a pattern “1”. In this instance, the information of PLP_TI_CELLINV_START may be mainly set to subsequent interleaving pattern order information “2” without using “1”. In other words, cell interleaving pattern information may be set to subsequent interleaving pattern order information of pattern information obtained at the same location as that of the FEC block location information.

FIG. 50 illustrates a configuration of a CDI according to an embodiment of the present invention. A CDI included in a broadcast signal reception apparatus may operate in reverse order of a broadcast signal transmission apparatus. An output signal of the CDI may be expressed by output cells. As described in the foregoing, the time deinterleaver of the present invention may perform cell deinterleaving after performing convolutional deinterleaving in the S-PLP mode. In other words, an input signal or input cells of the cell deinterleaver may be defined as an output signal or output cells of the CDI. The CDI may perform FIFO processing on input cells. Here, a memory unit or a deinterleaving unit included in the CDI may store one cell or two or more contiguous cells together. In other words, the memory unit or the deinterleaving unit included in the CDI may store a pair of cells. Here, the two or more cells may be contiguous cells. In the figure, M_i,j denotes a memory included in the CDI, and subscripts i and j may indicate an ith row and a jth column. In addition, the CDI may include N_row rows and N_column columns. N_cell may denote the number of cells subjected to cell deinterleaving or a size of an FEC block.

FIG. 51 illustrates an operation method of a convolutional deinterleaver according to an embodiment of the present invention. Presumptions in the operation of the convolutional interleaver described above are similarly applied to the convolutional deinterleaver to be described below, and it can be presumed that frame synchronization is performed from a second frame and accurate signaling information is detected. As illustrated in the figure, the convolutional deinterleaver may receive and use signaling information corresponding to at least one of PLP_TI_NUM_ROW_MAX which is maximum row size information, PLP_TI_NUM_ROW which is row size information, PLP_TI_START_ROW which is location information of a row to which a first cell is input, PLP_TI_CELLINV_START which is cell interleaving pattern information, and/or PLP_TI_FECBLOCK_START which is FEC block location information. As illustrated in the figure, a broadcast signal reception apparatus may receive signaling information in which PLP_TI_NUM_ROW_MAX is set to 4, PLP_TI_NUM_ROW is set to 4, PLP_TI_START_ROW is set to 2, PLP_TI_CELLINV_START is set to 2, and PLP_TI_FECBLOCK_START is set to 2.

First, a configuration of the convolutional deinterleaver may use at least one of PLP_TI_NUM_ROW_MAX and/or PLP_TI_NUM_ROW. In other words, a value of PLP_TI_NUM_ROW_MAX and/or PLP_TI_NUM_ROW is set to 4, and thus N_row may be set to 4 and N_column may be set to 3 in the configuration of the convolutional deinterleaver since N_column may be obtained by N_row−1. A specific operation of the convolutional deinterleaver will be described with reference to a subsequent figure.

FIG. 52 illustrates an operation method of a convolutional deinterleaver according to an embodiment of the present invention. As described in the foregoing, it can be presumed that frame synchronization is performed from a second frame in the convolutional deinterleaver. A description will be given of the operation method of the convolutional deinterleaver using a second frame output to the above-described convolutional interleaver. As illustrated in the figure, the convolutional deinterleaver may operate using PLP_TI_START_ROW and PLP_TI_FECBLOCK_START. In other words, the convolutional deinterleaver may input a first cell to row 2 using information of PLP_TI_START_ROW=2. In addition, after interleaving, a first complete FEC block may start from a second cell with respect to a CDI output signal using information of PLP_TI_FECBLOCK_START=2. Thereafter, after interleaving, the cell deinterleaver may perform cell deinterleaving of the first complete FEC block using a second interleaving pattern based on information of PLP_TI_CELLINV_START.

Hereinafter, a description will be given of signaling information used for time interleaving according to another embodiment of the present invention. The signaling information used for time interleaving may be delivered from a broadcast signal transmission apparatus to a broadcast signal reception apparatus through L1 signaling. L1 signaling information included in L1 signaling may include static signaling and dynamic signaling. TI signaling information to be described below may be delivered to the broadcast signal reception apparatus through static signaling or dynamic signaling included in L1 signaling.

FIG. 53 illustrates a time interleaver according to an embodiment of the present invention. In other words, FIG. 53(a) illustrates a configuration of a time interleaver according to a PLP mode in a broadcast signal transmission system according to an embodiment of the present invention. As described in the foregoing, the time interleaver may include a twisted BI and a convolutional delay line in a multiple-PLP (M-PLP) mode. As described above, the convolutional delay line may be referred to as a convolutional interleaver. The time interleaving including the twisted BI and the convolutional delay line may be referred to as a hybrid TI. On the other hand, in a single-PLP (S-PLP) mode, only an arbitrary CI may be used.

A (modified) cell interleaver may be applied to both the S-PLP & M-PLP modes, and have the same operation and specific characteristic or a different operation and specific characteristic according to a given PLP mode.

Each block included in the TI may operate using TI signaling information. In other words, as illustrated in the figure, the cell interleaver, the twisted BI, the convolutional delay line, and the CI included in the TI may operate according to TI signaling information. The TI signaling information may include configurable signaling and dynamic signaling.

FIG. 53(b) is a block diagram equivalently illustrating a time interleaver according to an embodiment of the present invention. The time interleaver may have the same configuration as that of the above-described time interleaver. The time interleaver may include a twisted BI and a convolutional delay line in an M-PLP mode and include an arbitrary CI in an S-PLP mode. In addition, the TI may further include a cell interleaver in each PLP mode. As illustrated in the figure, TI signaling may deliver information related to operations of the cell interleaver, the twisted BI, the convolutional delay line, and the CI included in the TI, and may include configurable signaling and dynamic signaling. In addition, when the time interleaver includes another interleaver in each PLP mode, TI signaling information may be delivered to the corresponding interleaver.

The present invention may describe a definition of signaling information necessary for an operation of each block included in the TI.

FIG. 54 illustrates a portion of time interleaving signaling information according to an embodiment of the present invention. TI signaling information may include a configurable signaling field and a dynamic signaling field. Information included in the configurable signaling field may be described with reference to FIG. 54. The configurable signaling field may include TI signaling information having a constant value in a super-frame. In other words, information included in the configurable signaling field may be changed using a super-frame as a unit and not be changed in the same super-frame. The configurable signaling field may be separately signaled in the S-PLP mode and the M-PLP mode according to NUM PLP that indicates the number of PLPs.

Signaling information for an operation of the CI of the S-PLP mode may include PLP_TI_NUM_ROW_MAX, PLP_TI_ROW_SIZE, PLP_TI_START_ROW and/or PLP_TI_FECBLOCK_START. In addition, the signaling information for the operation of the CI of the S-PLP mode may further include FRAME_INTERVAL. A definition of signaling will be described below in detail. In this instance, additional signal information may be added to the configurable signaling field for the S-PLP mode to support a flexible operation of the CI.

PLP_TI_NUM_ROW_MAX is information indicating a maximum number of delay lines included in the CI, and each delay line may be expressed by a row.

PLP_TI_NUM_ROW is information indicating the number of delay lines included in the CI, and each delay line may be expressed by a row.

PLP_TI_START_ROW is information indicating a start position of a switch of the time deinterleaver, and may indicate a row from which the switch starts deinterleaving in a starting part of an FEC frame. In other words, PLP_TI_START_ROW may be information indicating a location of an interleaver selector in a starting part of a signal frame. In the present specification, a switch of a deinterleaver may be expressed by a selector or a commutator. In the present specification, PLP_TI_START_ROW may be expressed by L1D_CI_start_row.

PLP_TI_FECBLOCK_START is information indicating a start position of a first complete FEC block in an ATSC signal frame. In the present specification, an FEC block related to the S-PLP mode may be referred to as an FEC frame, and PLP_TI_FECBLOCK_START may be expressed by L1D_CI_fecframe_start.

FRAME_INTERVAL will be described below in the M-PLP mode.

Signaling information necessary to operate a hybrid TI of an M-PLP mode corresponds to PLP_NUM_BLOCKS_MAX, TIME_IL_LENGTH, TIME_IL_TYPE, FRAME_INTERVAL, etc., and a definition of signaling will be described below in detail.

PLP_NUM_BLOCKS_MAX is information indicating a maximum number of FEC blocks. In other words, PLP_NUM_BLOCKS_MAX may indicate a maximum number of FEC blocks per interleaving frame for a current PLP.

TIME_IL_TYPE corresponds to a 1-bit field, and may correspond to information indicating a type or a mode of time interleaving. In the present specification, TIME_IL_TYPE may be referred to as L1D_HTI_inter_frame. When a value of TIME_IL_TYPE is set to 0, the value may indicate that inter-frame interleaving is not used and intra-frame interleaving is used. Here, an interleaving frame may include one or a plurality of TI blocks. When TIME_IL_TYPE is set to 1, the value may indicate that inter-frame interleaving is used, and one interleaving frame may include one TI block. In addition, one TI block included in an interleaving frame may be spread over a plurality of ATSC broadcast signal frames.

TIME_IL_LENGTH may be defined as below according to TIME_IL_TYPE described above. In the present specification, TIME_IL_LENGTH may be indicated by L1D_HTI_num_ti_blocks. When a value of TIME_IL_TYPE is set to 1, TIME_IL_LENGTH may refer to P I that indicates the number of frames. Here, the number of frames may refer to the number of conveyed frames when a memory unit included in one TI block is spread by time interleaving.

When a value of TIME_IL_TYPE is set to 0, TIME_IL_LENGTH corresponds to information indicating N_TI which is the number of TI blocks per interleaving frame, and may indicate the number of TI blocks included in one interleaving frame.

When one TI block is included per interleaving frame and one signal frame is present per interleaving frame, TIME_IL_LENGTH may be set to 1 and TIME_IL_TYPE may be set to 0. When time interleaving is not used for a PLP, TIME_IL_LENGTH may be set to 0 and TIME_IL_TYPE may be set to 0.

FRAME_INTERVAL is information indicating I_JUMP which is an ATSC frame interval. FRAME_INTERVAL may indicate an ATSC frame interval in a super-frame for a linked PLP. In addition, FRAME_INTERVAL may indicate a distance between two ATSC frames that convey memory units included in one TI block. For PLPs that appear in some frames rather than every frame in a super-frame, FRAME_INTERVAL may have the same value as an interval between contiguous frames. As an example, when a certain PLP belongs to frame 1, frame 4 and frame 7, a value of FRAME_INTERVAL may be set to 3. As another example, when a certain PLP appears in every frame, a value of FRAME_INTERVAL may be set to 1.

FIG. 55 illustrates the other portion of the time interleaving signaling information according to an embodiment of the present invention. TI signaling information may include a configurable signaling field and a dynamic signaling field. Information included in the dynamic signaling field may be described with reference to FIG. 55. The dynamic signaling field may include TI signaling information having a constant value in one frame. Information included in the dynamic signaling field may be changed for every frame. In other words, the information included in the dynamic signaling field may be changed using a frame as a unit and may not be changed in the same frame. The dynamic signaling field may be separately signaled in the S-PLP mode and the M-PLP mode according to NUM PLP that indicates the number of PLPs.

Signaling information for an operation of the CI of the S-PLP mode may include PLP_TI_NUM_ROW, PLP_TI_START_ROW and/or PLP_TI_FECBLOCK_START. A definition of signaling will be described below in detail. Here, information of PLP_TI_NUM_ROW, PLP_TI_START_ROW, and PLP_TI_FECBLOCK_START may not be used or may not be defined when a configuration and an operation of the CI are not changed for every frame.

PLP_TI_NUM_ROW is information indicating the number of delay lines included in the CI, and each delay line may be expressed by a row.

PLP_TI_START_ROW is information indicating a start position of a switch of the time deinterleaver, and may indicate a row from which the switch starts deinterleaving in a starting part of an FEC frame. In the present specification, a switch of a deinterleaver may be expressed by a selector or a commutator. In the present specification, PLP_TI_START_ROW may be expressed by L1D_CI_start_row.

PLP_TI_FECBLOCK_START is information indicating a start position of a first complete FEC block in an ATSC signal frame. In the present specification, an FEC block related to the S-PLP mode may be referred to as an FEC frame, and PLP_TI_FECBLOCK_START may be expressed by L1D_CI_fecframe_start.

Signaling information necessary to operate a hybrid TI of an M-PLP mode may include PLP_NUM_BLOCKS. PLP_NUM_BLOCKS may be a field to which 8 bits are allocated. PLP_NUM_BLOCKS may indicate information that indicates the number of FEC blocks included in an interleaving frame for a current PLP. In the present specification, PLP_NUM_BLOCKS may be expressed by L1D_HTI_num_fec_blocks.

FIG. 56 illustrates a time deinterleaver according to an embodiment of the present invention. In other words, FIG. 56(a) illustrates a configuration of a time deinterleaver according to a PLP mode in a broadcast signal reception system according to an embodiment of the present invention. As described in the foregoing, the time deinterleaver may include a convolutional delay line and a twisted BDI in an M-PLP mode. In the present specification, the convolutional delay line included in the time deinterleaver may perform inverse processing of the convolutional delay line included in the time interleaver. The time deinterleaver including the convolutional delay line and the twisted BDI may be referred to as a hybrid TDI. On the other hand, in an S-PLP mode, only an arbitrary CDI may be used.

A (modified) cell deinterleaver may be applied to both the S-PLP & M-PLP modes, and have the same operation and specific characteristic or a different operation and specific characteristic according to a given PLP mode.

Each block included in the TDI may operate using TI signaling information. In other words, as illustrated in the figure, the cell deinterleaver, the twisted BDI, the convolutional delay line, and the CDI included in the TDI may operate according to TI signaling information. The TI signaling information may include configurable signaling and dynamic signaling. The TI signaling information received and used by the TDI is the same as the TI signaling information transmitted by the broadcast signal transmission apparatus described above and may be received by a broadcast signal reception apparatus through L1 signaling.

FIG. 56(b) is a block diagram equivalently illustrating a time deinterleaver according to an embodiment of the present invention. The time deinterleaver may have the same configuration as that of the above-described time deinterleaver. The time deinterleaver may include a twisted BDI and a convolutional delay line in the M-PLP mode and include an arbitrary CDI in the S-PLP mode. In addition, the TDI may further include a cell deinterleaver in each PLP mode. As illustrated in the figure, TI signaling may deliver information related to operations of the cell deinterleaver, the twisted BDI, the convolutional delay line, and the CDI included in the TDI, and may include configurable signaling and dynamic signaling. In addition, when the time deinterleaver includes another deinterleaver in each PLP mode, TI signaling information may be delivered to the corresponding deinterleaver. The TI signaling information received and used by the TDI is the same as the TI signaling information transmitted by the broadcast signal transmission apparatus described above and may be received by a broadcast signal reception apparatus through L1 signaling.

FIG. 57 illustrates a portion of a configuration of a broadcast signal transmission apparatus with respect to a next generation broadcast service according to another embodiment of the present invention.

An illustrated bit interleaved coded modulation (BICM) encoder may correspond to the above-described coding and modulation module. In the present embodiment, the BICM encoder may include an FEC encoder, a bit interleaver and/or a constellation mapper. A framing & interleaving module illustrated in the figure may correspond to a new concept that collectively refers to the time interleaver, the frame builder and/or the frequency interleaver described above. Here, the frame builder may be referred to as a framer.

According to a given embodiment, the time interleaver may be included in the BICM encoder rather than the framing & interleaving module. In this case, the framing & interleaving module may not include the time interleaver. In addition, the time interleaver in the BICM encoder may be positioned after the constellation mapper. According to another embodiment, the time interleaver may be positioned between the BICM encoder and the framing & interleaving module. In this case, the framing & interleaving module may not include the time interleaver.

In a broadcast signal transmission apparatus with respect to the next generation broadcast service according to another embodiment of the present invention, the above-described cell interleaver may be included in the time interleaver. In other words, the time interleaver according to the present embodiment may include a cell interleaver, a block interleaver, and/or a convolutional interleaver. The block may be omitted or replaced by another block having a similar or the same function.

The present invention proposes a scheme of performing interleaving by grouping cells into one or two units according to a modulation order. Here, the grouped cells may be used in the above-described time interleaving process. The grouped cells may be block-interleaved by being used as an input of the block interleaver, and then convolutional-interleaved. According to a given embodiment, the grouped cells may be convolutional-interleaved by being used as an input of the convolutional interleaver. Here, when two cells are grouped, two contiguous cells may become a target for grouping. Interleaving targeted for the grouped cells may be referred to as pair-wise interleaving or extended interleaving. The grouped cells may be referred to as a memory unit (MU). In addition, the present invention proposes a scheme of performing deinterleaving by grouping cells into one or two units. Deinterleaving may be an operation on a receiving side corresponding to the proposed pair-wise interleaving, and performed in a reverse order of an operation on a transmitting side.

FIG. 58 illustrates possible configurations of a time interleaver according to another embodiment of the present invention.

As described in the foregoing, the cell interleaver may be included in the time interleaver. As described above, the time interleaver according to the present embodiment may include a cell interleaver, a block interleaver, and/or a convolutional interleaver. According to a given embodiment, an internal configuration of the time interleaver may be changed. A possible internal configuration of the time interleaver is illustrated. However, the present invention is not limited thereto, and the internal configuration of the time interleaver may be changed within the scope of the present invention.

A first configuration t2010 of the time interleaver may be an internal configuration of the time interleaver in a case of one PLP, that is, S-PLP. In this case, the time interleaver may include a cell grouping module for performing cell groping for convolutional interleaving, and a convolutional interleaver. Here, the cell grouping module may be referred to as a cell-to-memory unit mapper. After convolutional interleaving is performed, a memory unit-to-cell demapper on the inside/outside of the time interleaver may demap the cells grouped into the MU to cells (this block is not illustrated). According to a given embodiment, the time interleaver may or may not include the cell interleaver.

A second configuration t2020 of the time interleaver may be an internal configuration of the time interleaver in a case of a plurality of PLPs, that is, M-PLP. In this case, the time interleaver may include a cell grouping module for performing cell grouping for block interleaving and convolutional interleaving, a block interleaver, and/or a convolutional interleaver. Similarly, after convolutional interleaving is performed, demapping from the MU to the cells may be performed. According to a given embodiment, the time interleaver may or may not include the cell interleaver.

When the above-described pair-wise interleaving is not performed, that is, when one cell corresponds to one MU, the cell-to-memory unit mapper and/or the memory unit-to-cell demapper may not be included in the time interleaver.

The number of PLPs may be obtained through a field value of PLP_NUM corresponding to a related signaling field. When PLP_NUM is 1, the number of PLPs may be 1.

Here, prior to block interleaving, the cell interleaver may interleave cells in FEC blocks such that cells are output in different orders between FEC blocks. An operation of the cell interleaver may greatly enhance time diversity performance of the time interleaver. The cell interleaver may perform cell interleaving by linearly writing cells to a memory and randomly reading cells using a pseudorandom sequence. The block interleaver may block-interleave a TI block including at least one FEC block. The block interleaver may perform interleaving by linearly writing MUs in an FEC block to a memory in a column direction and diagonally reading MUs. In this instance, a write operation may be performed such that virtual MUs are positioned before actual MUs on the memory. The virtual MUs may be skipped in a read operation. The convolutional interleaver may perform interleaving by dispersing block-interleaved TI blocks into a plurality of signal frames. The convolutional interleaver may correspond to a convolutional delay line or an arbitrary convolutional interleaver.

FIG. 59 illustrates a cell grouping process according to an embodiment of the present invention.

When pair-wise interleaving is not performed, one cell may correspond to one MU. In this case, the cell-to-memory unit mapper and/or the memory unit-to-cell demapper described above may be omitted. The block interleaver may write one cell (=one MU) to a memory. Thereafter, the block interleaver may read the written cell (=one MU). Write and read operations may be performed according to the above-described scheme. In this case, the number N_(r) of memory rows may be the same as the number N_(cells) of cells in an FEC block. A case in which pair-wise interleaving is not performed may be referred to as single-wise grouping or single-wise interleaving.

When pair-wise interleaving proposed in the present invention is performed, two contiguous cells may correspond to one MU. The above-described cell-to-memory unit mapper may map two contiguous cells in an FEC block to one MU. The block interleaver may write the two contiguous cells (=one MU) to a memory. Thereafter, the block interleaver may read the written cell pair (=one MU). Write and read operations may be performed according to the above-described scheme. In this case, the number N_(r) of memory rows may be the same as half the number N_(cells) of cells in an FEC block.

FEC blocks t3010 to be subjected to cell grouping in pair-wise interleaving are illustrated. A first FEC block may include cells corresponding to indices of 0, 1, 2, 3, etc. In a state t3020 in which cell grouping is performed and cells are written to a memory by the block interleaver, two contiguous cells are stored in one space of a memory array. In other words, a number 0 cell and a number 1 cell may be paired and stored in the memory, and a number 2 cell and a number 3 cell may be paired and stored in the memory.

According to a given embodiment, an operation of mapping cells to an MU may be performed simultaneously with an operation of writing an MU to a memory by the block interleaver. In other words, the two operations may be simultaneously performed when two contiguous cells are mapped to one space of a memory array. Here, the one space of the memory array may be referred to as an MU.

In both single-wise interleaving and pair-wise interleaving, interleaving may be performed using an MU as a unit. However, an MU may correspond to one cell in single-wise interleaving, and an MU may correspond to a cell pair of two contiguous cells in pair-wise interleaving.

In pair-wise interleaving, two cells may be contained in one MU, and thus two cells may be written and read at the same position of the memory. As a result, interleaving depth doubles.

FIG. 60 illustrates a cell grouping scheme according to a modulation order according to an embodiment of the present invention.

As described in the foregoing, whether single-wise interleaving is performed or pair-wise interleaving is performed may be determined based on a modulation order. A modulation order may be determined based on a constellation used on a constellation mapper.

Pair-wise interleaving may be applied to a modulation order having a relatively small bit resolution such as QPSK, 16QAM, etc. due to a restrictive memory size of the time interleaver. A type of applied interleaving may be signaled by a signaling field. For example, a transmitting side may define a flag field of PAIRWISE_TI_FLAG to indicate whether pair-wise interleaving is performed. Pair-wise interleaving may be performed when the field has a value of 1, and single-wise interleaving may be performed instead of pair-wise interleaving when the field has a value of 0. As described in the foregoing, pair-wise interleaving may be referred to as extended interleaving.

According to an embodiment of the present invention, single-wise or pair-wise interleaving may be applied to QPSK and/or 16QAM, and single-wise interleaving may be applied to 64QAM, 256QAM, 1024QAM and/or 4096QAM. According to another embodiment of the present invention, pair-wise interleaving may be applied to QPSK, and pair-wise interleaving may not be applied to the other modulation orders.

FIG. 61 illustrates an operation of the block interleaver using cell grouping according to an embodiment of the present invention.

When pair-wise interleaving is used, two contiguous cells may be mapped to one MU by cell grouping. In a memory t5010 of the block interleaver illustrated in the figure, two contiguous cells may be stored in each of shaded data MUs. As described in the foregoing, this write operation may be performed column-wise. Virtual MUs which are not shaded in a virtual FEC block may be positioned before data MUs in a memory array. Thereafter, each of the MUs may be read in a diagonal direction by the above-described operation of the block interleaver. In this way, paired cells may be read at the same position of the memory (pair-wise interleaving). As described in the foregoing, the virtual MUs may be skipped and not read in the read operation.

A block interleaving operation using pair-wise grouping (interleaving) may be mathematically expressed as in the figure. Here, k denotes an index, N_(r) denotes the number of rows of the memory, N_(c) denotes the number of columns of the memory, N_(diff) denotes the number of virtual FEC blocks, (r_(k), c_(k)) denotes coordinates of each of the MUs on the memory array, t_(k) denotes a twisting parameter, and θ_(k) denotes a position of an MU. In particular, a portion corresponding to a if-clause t5020 indicated in the figure may be related to a portion in which virtual MUs are skipped and not read. When θ_(k) of an MU is less than N_(r)*N_(diff), the MU may be skipped during a read operation.

FIG. 62 illustrates possible configurations of a time deinterleaver according to another embodiment of the present invention.

The time deinterleaver according to the present embodiment may be a module on a receiving side corresponding to the above-described time interleaver according to another embodiment of the present invention. Here, the time deinterleaver may be included in a parsing & deinterleaving module. The parsing & deinterleaving module may be a new concept that collectively refers to a frequency deinterleaver, a frame parser and/or the time deinterleaver.

As described in the foregoing, a cell deinterleaver may be included in the time deinterleaver. As described in the foregoing, the time deinterleaver according to the present embodiment may include a convolutional deinterleaver, a block deinterleaver and/or a cell deinterleaver. According to a given embodiment, an internal configuration of the time deinterleaver may be changed. A possible internal configuration of the time deinterleaver is illustrated. However, the present invention is not limited thereto, and the internal configuration of the time deinterleaver may be changed within the scope of the present invention.

A first configuration t6010 of the timer deinterleaver may be an internal configuration of the timer deinterleaver in a case of one PLP, that is, S-PLP. In this case, the timer deinterleaver may include a convolutional deinterleaver and a cell parser. The cell parser may demap cells grouped to an MU and output cells again. Here, the cell parser may be referred to as a memory unit-to-cell demapper. Before convolutional interleaving is performed, a cell-to-memory unit mapper on the inside/outside of the time deinterleaver may group cells into an MU again (this block is not illustrated). According to a given embodiment, the timer deinterleaver may or may not include the cell deinterleaver.

A second configuration t6020 of the timer deinterleaver may be an internal configuration of the timer deinterleaver in a case of a plurality of PLPs, that is, M-PLP. In this case, the timer deinterleaver may include a convolutional deinterleaver, a block deinterleaver and/or a cell parser. The cell parser may be similar to the above-described cell parser. Similarly, before convolutional deinterleaving is performed, the cell-to-memory unit mapper on the inside/outside of the time deinterleaver may group cells into an MU again (this block is not illustrated). According to a given embodiment, the timer deinterleaver may or may not include the cell deinterleaver.

When the above-described pair-wise interleaving is not performed, that is, when one cell corresponds to one memory unit, the cell-to-memory unit mapper and/or the memory unit-to-cell demapper may not be included in the time deinterleaver.

The cell parser may determine whether pair-wise interleaving is performed based on an indication of the above-described PAIRWISE_TI_FLAG field. In this way, it is possible to perform an operation of demapping cells in the memory unit.

An operation and a configuration of the time deinterleaver may correspond to a reverse operation/reverse configuration of the time interleaver of the transmitter. Here, the convolutional deinterleaver may deinterleave an MU by performing an operation corresponding to a reverse operation of convolutional interleaving. The block deinterleaver may write an MU to a memory in a diagonal direction, and read an MU column-wise again. In this instance, the MU may be written to the memory based on a virtual MU of a virtual FEC block. The cell deinterleaver may perform deinterleaving for returning interleaved cells to original positions in one FEC block. An algorithm used at this time may be the same as an algorithm used in the transmitter.

FIG. 63 shows a mathematical expression of an operation of the block deinterleaver using cell grouping according to an embodiment of the present invention.

The operation of the block deinterleaver according to the present embodiment may correspond to a reverse operation of the operation of the block interleaver using cell grouping described above. The block deinterleaver may support single memory deinterleaving. That is, block deinterleaving may be performed by a single memory.

In the above described block interleaving operation, virtual MUs are skipped during the read operation. At the receiving side, block deinterleaving may be performed when the skipped virtual MUs are restored. In a case of a VBR service, the skipped virtual MUs may be restored before being written to a memory of the block deinterleaver at the transmitting side. After the virtual MUs are restored, MUs may be written in a diagonal direction, and MUs may be read column-wise, thereby performing deinterleaving.

FIG. 64 illustrates a configuration of layered division multiplexing (LDM) according to an embodiment of the present invention.

The present invention can propose a scheme of processing data using LDM at each PLP level, and a linked operation of the time interleaver according to the scheme. LDM may correspond to a constellation superposition technique that combines a plurality of data streams having different power levels. In LDM, an upper layer structure may be added to a basic transmitter configuration. In this way, LDM may enable different modulation and/or channel coding schemes in transmission through one RF channel.

The illustrated LDM configuration may include a BICM encoder t8010 according to a baseline layer, a BICM encoder t8020 according to an upper layer, an LDM injection module t8040 and/or a framing & interleaving module, and subsequent modules t8030. Here, the baseline layer may be referred to as a core layer, and the upper layer may be referred to as an enhanced layer. A configuration having two layers is proposed here. However, the present invention is not limited thereto, and may include a configuration having three or more layers based on subject matter of the present invention to be described below. Although not illustrated, input formatting modules according to the baseline and upper layers may be positioned in front of the BICM encoders according to the baseline and upper layers, respectively.

Each of the illustrated BICM encoders t8010 and t8020 may include an FEC encoder, a bit interleaver, and/or a constellation mapper. A bit-to-cell demultiplexer may be omitted. According to a given embodiment, the constellation mapper may be omitted. Operations of internal modules of the BICM encoders may be as described above.

The baseline layer (core layer) may be targeted for robust transmission in an environment having severe channel fading such as an indoor environment or a mobile reception environment. On the other hand, the upper layer (enhanced layer) may be used in an environment in which high-throughput transmission can be performed such as a fixed reception environment, etc. To this end, the baseline layer may use an MODCOD combination which is as robust as or more robust than that of the upper layer. The baseline layer may use a low-order constellation and a low code rate, and the upper layer may use a high-order constellation and a high code rate.

The illustrated LDM injection module t8040 may combine data subjected to processing such as FEC encoding, etc. in each layer. As illustrated in the figure, an internal configuration of the LDM injection module may include an injection level controller t8041, an adder, and/or a power normalization module t8042.

The injection level controller t8041 may adjust a power level of the upper layer in order to adjust a power ratio of the baseline layer to the upper layer. In this instance, a sum of transmission power of the baseline layer and transmission power of the upper layer may be adjusted to 1 (normalizing to unity). A power ratio of the upper layer to the baseline layer may be reduced by the injection level controller such that output transmission energy may have a desired bit rate. An injection level ratio of the upper layer to the baseline layer may be signaled by signaling information, etc. According to a given embodiment, the injection level controller t8041 may be positioned on a side of the baseline layer to adjust power of the baseline layer, thereby adjusting the power ratio of the upper layer to the baseline layer.

Thereafter, the adder may perform an operation of combining cells of each layer. The power normalization module t8042 may perform power normalization of combined data and output the data. The upper layer may be combined with the baseline layer before the time interleaver (or cell interleaver) based on complexity of the receiver.

LDM data (a DLM signal) obtaining by combining data of the baseline layer and data of the upper layer may pass through modules/blocks such as the above-described time interleaver, etc. In other words, subsequent modules may be shared by each layer. Therefore, interleaving depth may be unchanged thereafter. For example, the time interleaver may be shared by each layer, and the LDM data may be processed by the above-described time interleaver. In other words, as described in the foregoing, the time interleaver including the convolutional interleaver may be used in S-PLP, and the time interleaver including the cell interleaver, the block interleaver, and/or the convolutional interleaver may be used in M-PLP. The baseline layer and the upper layer may have the same PLP mode, that is, S-PLP mode or M-PLP mode. In the modules t8030 subsequent to the LDM injection module t8040 illustrated in the figure, the cell interleaver is positioned outside the time interleaver. However, according to a given embodiment, the cell interleaver may be positioned inside the time interleaver. Thereafter, additional processing such as framing, frequency interleaving, MISO (2D-eSFN), etc. may be selectively performed according to a given embodiment.

FIG. 65 illustrates a configuration of LDM on the receiving side according to an embodiment of the present invention.

The LDM configuration on the receiving side may correspond to a reverse operation of the LDM configuration on the transmitting side described above. The upper layer may need to be cancelled first to decode the baseline layer. To this end, sufficient reception SNR margin may be needed between respective layers. In an example illustrated in the figure, the upper layer is decoded first, and interference by the upper layer is cancelled from the baseline layer using the decoded upper layer, thereby decoding the baseline layer. However, according to a given embodiment, the baseline layer may be decoded first, and then interference by the baseline layer may be cancelled using the decoded baseline layer, thereby decoding the upper layer.

In the illustrated LDM configuration on the receiving side, time deinterleaving may be performed by the time deinterleaver after processing such as MISO decoding, frame parsing, etc. In the illustrated example, the cell deinterleaver is positioned outside the time deinterleaver. However, the cell deinterleaver may be positioned inside the time deinterleaver.

First, data corresponding to the upper layer may be decoded (t9010). This decoding process may be performed through a constellation demapper, a bit deinterleaver, and/or an FEC decoder as in the above-described BICM decoder. Here, a cell-to-bit multiplexer may be omitted. Through the process, the data corresponding to the upper layer may be decoded and output (t9060).

Thereafter, an interference cancellation operation may be performed to decode data corresponding to the baseline layer. The decoded data of the upper layer (t9060) may be encoded/modulated again (t9020). This process may be performed by the bit interleaver and/or the constellation mapper. Here, the bit-to-cell demultiplexer may be omitted. Through this process, it is possible to synchronize with the baseline layer.

The data corresponding to the baseline layer may be delivered to an FEC block buffer after time deinterleaving, and wait until an upper layer side is decoded (t9030). Referring to the data corresponding to the baseline layer of the FEC block buffer, interference by the upper layer may be cancelled using the data of the upper layer encoded/modulated again (t9040).

After interference is cancelled, an operation of restoring the data of the baseline layer may be performed (t9050). The operation may be performed through the constellation demapper, the bit deinterleaver, and/or the FEC decoder as in the above-described BICM decoder. Here, a cell-to-bit demultiplexer may be omitted. Through the operation, the data corresponding to the baseline layer may be decoded and output without interference by the upper layer (t9070).

In the illustrated restoration operation of the baseline layer (t9050), an additional buffer may be positioned before the bit deinterleaver. The FEC block buffer may be used to wait until the upper layer is completely decoded. However, the additional buffer may be used such that the upper layer and the baseline layer have the same FEC synchronization. In this way, it is possible to adjust an FEC size for the bit deinterleaver and the FEC decoder. A position of the additional buffer may be changed according to a given embodiment.

The decoded data of the upper layer and the decoded data of the baseline layer (t9060, t9070) may be processed by output formatting modules for the respective layers thereafter. In the illustrated LDM configuration on the receiving side, the constellation mapper and the constellation demappers may be omitted according to a given embodiment.

FIG. 66 illustrates the convolutional interleaver in S-PLP according to an embodiment of the present invention.

First, an input of the convolutional interleaver in the time interleaver may correspond to a sequence of the MUs described above. The input may be expressed by g_(q). As described in the foregoing, in S-PLP, the time interleaver may include the convolutional interleaver. When pair-wise interleaving is used in S-PLP according to a given embodiment, the time interleaver may include the cell-to-memory unit mapper, the convolutional interleaver, and/or the memory unit-to-cell demapper.

The convolutional interleaver may include delay lines corresponding to N_(rows) rows. Here, a kth line may include k memory unites (k=0, 1, . . . , N_(rows)−1). Here, a memory unit may refer to a delay element that stores input MUs on a delay line. The number of rows N_(columns) of the convolutional interleaver may be N_(rows)−1. An input and an output may be controlled by two commutators. The commutators may be switched downward in a cyclic manner after one symbol is written or read. In other words, after one symbol/data is written or read in a state in which the commutators are switched up to a lowest row, the commutators may be switched to a first row again. The two commutators may be at the same position k in each cycle. Here, the total number of memory units may be N_(rows)*(N_(rows)−1)/2.

When an input commutator is at the position k, g_(q) corresponding to an input MU may be written to a kth delay line. For this process, first, delay elements on the kth delay line may shift stored memory content (data) to right delay elements. A rightmost delay element on the kth delay line may output stored data through an output commutator. Thereafter, g_(q) corresponding to the input MU may be written to a leftmost delay element on the kth delay line. In this way, FIFO processing may be performed. After the write operation, the two commutators may be cyclically shifted to a (k+1 modulo N_(rows))th line.

As described in the foregoing, an MU may include one or two cells. When two or more cells are included in the MU, interleaving depth may increase. A row size of the convolutional interleaver may be determined by signaling. In an LDM system, the time interleaver is shared, and thus respective layers may experience the same depth of the convolutional interleaver.

FIG. 67 illustrates signaling information for the convolutional interleaver in S-PLP according to an embodiment of the present invention.

The present invention proposes four signaling information, and the signaling information may be used even when LDM is used.

PLP_NUM_TI_ROWS may indicate a row size of the convolutional interleaver, that is, N_(rows). When the row size is signaled, a whole configuration of the convolutional interleaver may be determined. A value of this field may be determined according to PLP, and delivered through a configurable part of L1 post or a static part of PLS2. The field may have a length of 2 bits. As illustrated in the figure, it is possible to signal information indicating that 1024 rows are included in the convolutional interleaver when the field has a value of 00, 887 rows are included in the convolutional interleaver when the field has a value of 01, 724 rows are included in the convolutional interleaver when the field has a value of 10, and 512 rows are included in the convolutional interleaver when the field has a value of 11 (t11010). The receiving side may be aware of the configuration of the convolutional interleaver through the field.

PLP_TI_START_ROW may indicate a position of a selector (commutator) of the convolutional interleaver at a starting point of a transmitted signal frame. This field has a value that varies according to signal frames, and thus may be delivered through a dynamic part of L1 post or a dynamic part of PLS2. The field may have a length of 11 bits. At the receiving side, a first cell of a signal frame may be positioned at an appropriate commutator of the convolutional deinterleaver through the field.

PLP_TI_FECFRAME_START_LL may indicate a starting point of an FEC frame of a first complete upper layer of a transmitted signal frame. In other words, a starting point of a first FEC frame passing through the upper layer may be indicated by this field. The starting point may be indicated in a form of a cell index. The field has a value that varies according to signal frames, and thus may be delivered through a dynamic part of L1 post or a dynamic part of PLS2. The field may have a length of 15 bits. The receiving side may be aware of the starting point of the first FEC frame of the upper layer through the field.

Several conditions need to be satisfied to signal an FEC frame that completely appears in current and subsequent signal frames. When a starting point indicated by this field is referred to as n, a row index for an nth cell of a signal frame may be referred to as Rs. Rs may be defined as a value obtained by calculating (PLP_TI_FECFRAME_START+PLP_TI_START_ROW) modulo N_(rows). In this instance, the above-described conditions may be satisfied when PLP_TI_FECFRAME_START is greater than or equal to Rs*(N_(rows)+1). When the starting point of the FEC frame does not satisfy the above-described conditions, in other words, when a cell included in the same FEC frame is included in a previously transmitted signal frame, whether a starting point of a subsequent FEC frame satisfies the above-described conditions may be verified, which may be due to a delaying property of the convolutional interleaver.

PLP_TI_FECFRAME_START_UL may indicate a starting point of an FEC frame of a first complete baseline layer of a transmitted signal frame. This field is the same as PLP_TI_FECFRAME_START_LL described above except that this field is related to the baseline layer. Layers indicated by both the fields may be changed according to embodiments. Starting points of FEC frames of the respective layers may be different from each other.

FIG. 68 illustrates a method of transmitting a broadcast signal according to an embodiment of the present invention.

The method of transmitting the broadcast signal according to the present embodiment may include encoding data in a plurality of PLPs, processing the encoded data in the plurality of PLPs, and/or performing waveform modulation and transmission.

In the present embodiment, the above-described encoder may encode the data in the plurality of PLPs (t12010). Here, PLP may be referred to as DP. In addition, the encoder may correspond to the above-described BICM encoder. According to a given embodiment, the BICM encoder may include an FEC encoder, a bit interleaver, and/or a constellation mapper. According to a given embodiment, the BICM encoder may not include the cell interleaver and the time interleaver.

The encoded data in the plurality of PLPs may be processed by a framing & interleaving block (t12020). Here, the framing & interleaving block is as described above. At least one signal frame may be output by this processing. According to a given embodiment, processing the encoded data by the framing & interleaving block may include time-interleaving the data in the plurality of PLPs by the time interleaver, frame-mapping the time-interleaved data to at least one signal frame by a framer, and/or frequency-interleaving data of the signal frame by a frequency interleaver.

Thereafter, the above-described data of the at least one signal frame may be modulated by waveform modulation (t12030). Waveform modulation may be performed by a waveform generation block, which may be an OFDM module, a waveform module, etc. according to a given embodiment. The broadcast signal which includes the waveform-modulated data may be transmitted by an operation of the waveform generation block. The waveform generation block may include at least one antenna according to a given embodiment.

In a method of transmitting a broadcast signal according to another embodiment of the present invention, the encoding of the data in the plurality of PLPs described above may include encoding data in at least one PLP of a first layer and/or encoding data in a remaining PLP of a second layer. PLP encoding may be performed for each layer according to the above-described LDM configuration. With respect to two or more layers, encoding may be performed for PLP corresponding to each layer. According to a given embodiment, one PLP or one or more PLPs may be encoded in each layer. Encoding in each layer may be performed by a first encoder and a second encoder in the encoder.

A method of transmitting a broadcast signal according to another embodiment of the present invention may include combining the first layer and the second layer together. The combining may be performed by an injection block or an LDM injection block. The combining may be performed prior to time interleaving. Data encoded in the first layer and the second layer may be combined by the injection block before being subjected to time interleaving.

In a method of transmitting a broadcast signal according to another embodiment of the present invention, the combining may include controlling an injection level of the second layer, combining the first layer and the controlled second layer, and/or normalizing total power of the combined data. Here, each operation may be performed by an injection level controller, an adder, and/or a power normalizer. Here, controlling of the injection level of the second layer may be performed by reducing power of the second layer relative to the first layer.

In a method of transmitting a broadcast signal according to another embodiment of the present invention, encoding performed in the first layer may be more robust than encoding performed in the second layer. To this end, a combination of parameters in the first and second layers may be determined. Here, the combination of parameters may refer to modulation and/or a code rate, that is, MODCOD, etc.

In a method of transmitting a broadcast signal according to another embodiment of the present invention, time interleaving may include convolutional interleaving. Convolutional interleaving may be performed by the convolutional interleaver. In other words, the time interleaver may include the convolutional interleaver. A configuration of the time interleaver may be a configuration corresponding to a case in which LDM is used. Convolutional interleaving may be performed by the combined data of the first and second layers.

In a method of transmitting a broadcast signal according to another embodiment of the present invention, the first layer may correspond to the above-described core layer, and the second layer may correspond to the above-described enhanced layer.

In a method of transmitting a broadcast signal according to another embodiment of the present invention, the time-interleaving by the above-described time interleaver may include cell-interleaving data in PLP by the cell interleaver, block interleaving data in PLP by the block interleaver, and/or convolutional-interleaving data in PLP by the convolutional interleaver. The cell interleaver, the block interleaver, and/or the convolutional interleaver may be included in the above-described time interleaver. A configuration of the time interleaver may be a configuration corresponding to a case in which LDM is not used. The configuration of the time interleaver may be a configuration used in a case of a plurality of PLPs.

In a method of transmitting a broadcast signal according to another embodiment of the present invention, the block-interleaving may include writing an FEC block to a memory column-wise, and reading MUs of the written FEC block diagonal-wise. In the write operation, a virtual FEC block may be positioned in front of the actually written FEC block on the memory. In the read operation, virtual MUs of the virtual FEC block may not be read and skipped.

In a method of transmitting a broadcast signal according to another embodiment of the present invention, each MU may include one or two contiguous cells. This may be determined according to modulation order in constellation mapping.

A description will be given of a method of receiving a broadcast signal according to an embodiment of the present invention. The method is not illustrated in the figure.

The method of receiving the broadcast signal according to the present embodiment may include receiving a broadcast signal and modulating a waveform, processing data in a signal frame, and/or decoding data in PLP.

First, a waveform block may receive a broadcast signal having at least one signal frame. The waveform block may be a block on the receiving side corresponding to a waveform generation block on the transmitting side. The waveform block may demodulate data in the signal frame.

Thereafter, a parsing & deinterleaving block may process the demodulated data in the at least one signal frame. The parsing & deinterleaving block may be a block on the receiving side corresponding to a framing & interleaving block on the transmitting side. The parsing & deinterleaving block may perform a reverse operation of the framing & interleaving block. A plurality of PLPs may be output by this operation. The processing by the parsing & deinterleaving block may include frequency-deinterleaving the data in the at least one signal frame by a frequency deinterleaver, frame-parsing PLP from the at least one signal frame by a frame parser, and/or time-deinterleaving the data in PLP by a time deinterleaver. In other words, the parsing & deinterleaving block may include a frequency deinterleaver, a frame parser, and/or a time deinterleaver. The frequency deinterleaver, the frame parser, and/or the time deinterleaver are modules on the receiving side corresponding to the frequency interleaver, the framer, and the time interleaver on the transmitting side, and may perform a reverse operation of the respective modules on the transmitting side.

Thereafter, a decoder may decode data in the plurality of PLPs. Here, the decoder may be a block on the receiving side corresponding to the encoder or the BICM encoder on the transmitting side. The decoder may include a constellation demapper, a bit deinterleaver, and/or an FEC decoder.

A method of receiving a broadcast signal according to another embodiment of the present invention may further include splitting the time-deinterleaved data into a first layer and a second layer. This operation may be performed before decoding is performed for each layer. This operation may be performed by an LDM splitting block which is a module on the receiving side corresponding to the LDM injection block.

In a method of receiving a broadcast signal according to another embodiment of the present invention, the decoding may include decoding at least one PLP of the second layer, and decoding a remaining PLP of the first layer.

In a method of receiving a broadcast signal according to another embodiment of the present invention, the decoding of the remaining PLP of the first layer may include re-encoding the decoded second layer, cancelling interference by the second layer from the first layer using the re-encoded second layer, and decoding data of the first layer from which interference is cancelled. The respective steps may be performed by a re-encoder, an interference remover, and/or an inner decoder. The internal blocks may be included in the above-described LDM splitting block and a splitting block.

In a method of receiving a broadcast signal according to another embodiment of the present invention, encoding performed in the first layer may be more robust than encoding performed in the second layer. To this end, a combination of parameters in the first and second layers may be determined. Here, the combination of parameters may refer to modulation and/or a code rate, that is, MODCOD, etc.

In a method of receiving a broadcast signal according to another embodiment of the present invention, time deinterleaving may include convolutional deinterleaving. Convolutional deinterleaving may be performed by the convolutional deinterleaver. In other words, the time deinterleaver may include the convolutional deinterleaver. A configuration of the time deinterleaver may be a configuration corresponding to a case in which LDM is used. Convolutional deinterleaving may be performed before layer splitting.

In a method of receiving a broadcast signal according to another embodiment of the present invention, the first layer may correspond to the above-described core layer, and the second layer may correspond to the above-described enhanced layer.

In a method of receiving a broadcast signal according to another embodiment of the present invention, the time-deinterleaving may include convolutional-deinterleaving data in the plurality of PLPs by the convolutional deinterleaver, block-deinterleaving data in the plurality of PLPs by the block deinterleaver, and cell-deinterleaving data in the plurality of PLPs by the cell deinterleaver. A configuration of the time deinterleaver may be a configuration corresponding to a case in which LDM is not used. The configuration of the time deinterleaver may be a configuration used in a case of a plurality of PLPs.

In a method of receiving a broadcast signal according to another embodiment of the present invention, the block-deinterleaving may include writing an FEC block to a memory diagonal-wise, and reading MUs of the written FEC block column-wise. In the write operation, a virtual FEC block may be positioned in front of the actually written FEC block on the memory. In the read operation, virtual MUs of the virtual FEC block may not be read and skipped.

In a method of receiving a broadcast signal according to another embodiment of the present invention, each MU may include one or two contiguous cells. This may be determined according to modulation order in constellation mapping.

The above-described steps may be omitted according to a given embodiment, or replaced by other steps performing similar/the same operations.

FIG. 69 illustrates a broadcast signal transmission apparatus according to an embodiment of the present invention.

The broadcast signal transmission apparatus according to the present embodiment may include the encoder, the framing & interleaving block, and/or the waveform generation block described above. The time interleaver may include the cell interleaver, the block interleaver, and/or the convolutional interleaver. The encoder may include the FEC encoder, the bit interleaver, and/or the constellation mapper. The respective blocks and modules are as described above.

The broadcast signal transmission apparatus according to the present embodiment and internal modules/blocks thereof may perform the above-described embodiments of the method of transmitting the broadcast signal of the present invention.

A description will be given of a broadcast signal reception apparatus according to an embodiment of the present invention. The broadcast signal reception apparatus according to the present embodiment is not illustrated.

A broadcast content reception apparatus according to an embodiment of the present invention may include the waveform block, the frame parser, the time deinterleaver, and/or the decoder described above. The time deinterleaver may include the convolutional deinterleaver, the block deinterleaver, and/or the cell deinterleaver. The decoder may include the constellation demapper, the bit deinterleaver, and/or the FEC decoder. The respective blocks and modules are as described above.

The broadcast signal reception apparatus according to the present embodiment and internal modules/blocks thereof may perform the above-described embodiments of the method of receiving the broadcast signal of the present invention.

The internal blocks/modules, etc. of the broadcast signal transmission apparatus and the broadcast signal reception apparatus described above may correspond to processors that execute continuous operations stored in a memory, or hardware elements positioned inside/outside the apparatuses according to a given embodiment.

The above-described modules may be omitted according to a given embodiment or replaced by other modules that perform similar/the same operations.

Although the description of the present invention is explained with reference to each of the accompanying drawings for clarity, it is possible to design new embodiment(s) by merging the embodiments shown in the accompanying drawings with each other. And, if a recording medium readable by a computer, in which programs for executing the embodiments mentioned in the foregoing description are recorded, is designed in necessity of those skilled in the art, it may belong to the scope of the appended claims and their equivalents.

An apparatus and method according to the present invention may be non-limited by the configurations and methods of the embodiments mentioned in the foregoing description. And, the embodiments mentioned in the foregoing description can be configured in a manner of being selectively combined with one another entirely or in part to enable various modifications.

In addition, a method according to the present invention can be implemented with processor-readable codes in a processor-readable recording medium provided to a network device. The processor-readable medium may include all kinds of recording devices capable of storing data readable by a processor. The processor-readable medium may include one of ROM, RAM, CD-ROM, magnetic tapes, floppy discs, optical data storage devices, and the like for example and also include such a carrier-wave type implementation as a transmission via Internet. Furthermore, as the processor-readable recording medium is distributed to a computer system connected via network, processor-readable codes can be saved and executed according to a distributive system.

It will be appreciated by those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Both apparatus and method inventions are mentioned in this specification and descriptions of both of the apparatus and method inventions may be complementarily applicable to each other.

Various embodiments have been described in the best mode for carrying out the invention.

The present invention is available in a series of broadcast signal provision fields.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. 

1.-20. (canceled)
 21. A method of transmitting broadcast signals by an apparatus for transmitting broadcast signals, the method comprising: encoding first layer data; encoding second layer data; bit interleaving the encoded first layer data and the encoded second layer data, respectively; combining the bit interleaved first layer data and the bit interleaved second layer data with controlling an injection level of the bit interleaved second layer data, wherein the combined data is carried by at least one Physical Layer Pipe (PLP); time interleaving the combined data; frame mapping the time interleaved data onto at least one signal frame; frequency interleaving data in the at least one signal frame; waveform modulating, by a waveform generation block, the frequency interleaved data in the at least one signal frame; and transmitting the broadcast signals having the waveform modulated data.
 22. The method of claim 21, wherein the time interleaving is performed according to a mode for the time interleaving, wherein the mode of the second layer data is same as the mode of the first layer data.
 23. The method of claim 21, wherein the combining includes: reducing a power of the bit interleaved second layer data relative to the bit interleaved first layer data; combining the bit interleaved first layer data and the power-controlled second layer data; and normalizing total power of the combined data.
 24. The method of claim 23, wherein the combining the bit interleaved first layer data and the power-controlled second layer data is performed using injection level information, wherein the injection level information indicates the injection level of the second layer data relative to the first layer data.
 25. The method of claim 21, wherein the first layer data is encoded by using more robust combination of parameters than the second layer data.
 26. The method of claim 21, wherein the time interleaving includes: convolutional interleaving the combined data.
 27. The method of claim 21, wherein the first layer data is a core layer data, and the second layer data is an enhanced layer data.
 28. The method of claim 21, wherein the time interleaving includes: cell interleaving the combined data; block interleaving the cell interleaved data; and convolutional interleaving the block interleaved data.
 29. The method of claim 28, wherein the block interleaving includes: writing Forward Error Correction (FEC) blocks column-wise into a memory, wherein virtual FEC blocks are located ahead of the written FEC blocks in the memory; and diagonal-wise reading out the written FEC blocks from the memory by skipping the virtual FEC blocks.
 30. An apparatus for transmitting broadcast signals, the apparatus comprising: a first encoder to encode first layer data; a second encoder to encode second layer data; a bit interleaver to bit interleave the encoded first layer data and the encoded second layer data, respectively; an injection block to combine the bit interleaved first layer data and the bit interleaved second layer data with controlling an injection level of the bit interleaved second layer data, wherein the combined data is carried by at least one Physical Layer Pipe (PLP); a time interleaver to time interleave the combined data; a frame mapper to map the time interleaved data onto at least one signal frame; a frequency interleaver to frequency interleave data in the at least one signal frame; and a waveform generation block to modulate the frequency interleaved data in the at least one signal frame and to transmit the broadcast signals having the waveform modulated data.
 31. The apparatus of claim 30, wherein the time interleaver performs according to a mode for the time interleaving, wherein the mode of the second layer data is same as the mode of the first layer data.
 32. The apparatus of claim 30, wherein the injection block includes: an injection level controller to reduce a power of the bit interleaved second layer data relative to the bit interleaved first layer data; an adder to combine the bit interleaved first layer data and the power-controlled second layer data; and a power normalizer to normalize total power of the combined first and data.
 33. The apparatus of claim 32, wherein the adder combines the bit interleaved first layer data and the power-controlled second layer data using injection level information, wherein the injection level information indicates the injection level of the second layer data relative to the first layer data.
 34. The apparatus of claim 30, wherein the first layer data is encoded by using more robust combination of parameters than the second layer data.
 35. The apparatus of claim 30, wherein the time interleaver includes: a convolutional interleaver to convolutional interleave data in the combined data.
 36. The apparatus of claim 30, wherein the first layer data is a core layer data, and the second layer data is an enhanced layer data.
 37. The apparatus of claim 30, wherein the time interleaver includes: a cell interleaver to cell interleave the combined data; a block interleaver to block interleave the cell interleaved data; and a convolutional interleaver to convolutional interleave the block interleaved data.
 38. The apparatus of claim 37, wherein the block interleaver writes Forward Error Correction (FEC) blocks column-wise into a memory, wherein virtual FEC blocks are located ahead of the written FEC blocks in the memory, and diagonal-wisely reads out the written FEC blocks from the memory by skipping the virtual FEC blocks.
 39. (canceled)
 40. (canceled) 